EPM9560RI208-20N vs EPM9560RI208-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RI208-20N sa pamamagitan ng Intel at EPM9560RI208-20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RI208-20N | EPM9560RI208-20 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Device Family | MAX 9000 | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | — |
| Pin-to-Pin Delay | 20 ns (-20 speed grade) | — |
| Counter Speed | 100 MHz | — |
| Volte ng Pagbibigay | 5.0 V | — |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (IEEE Std. 1149.1 JTAG) |
| Packhaging | 208-pin RQFP | 208-pin RQFP (Power-Quad Flat Pack) 28x28 mm |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | Industrial (-40C to +85C) | [DATA_NEEDED: operating temperature range grade] |
| Development Tool | MAX+PLUS II | — |
| Design Entry | Schematic, VHDL, Verilog HDL, AHDL | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Packaging | Tray | — |
| Logic Architecture | Third-generation MAX (Multiple Array MatriX) | — |
| Fabrication Process | Advanced CMOS | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture | — | Multiple Array MatriX (MAX) - third generation |
| Macro Cells | — | 560 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Propagation Delay (tPD) | — | 20 ns |
| Counter Frequency (fCNT) | — | 100 MHz |
| Supply Voltage (VCC) | — | 5.0 V |
| Process Technology | — | CMOS EEPROM |