EPM9560RI208-20N vs EPM9560RI208-20 Comparison
Detailed side-by-side comparison of EPM9560RI208-20N by Intel and EPM9560RI208-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RI208-20N | EPM9560RI208-20 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Device Family | MAX 9000 | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | — |
| Pin-to-Pin Delay | 20 ns (-20 speed grade) | — |
| Counter Speed | 100 MHz | — |
| Supply Voltage | 5.0 V | — |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (IEEE Std. 1149.1 JTAG) |
| Package | 208-pin RQFP | 208-pin RQFP (Power-Quad Flat Pack) 28x28 mm |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | Industrial (-40C to +85C) | [DATA_NEEDED: operating temperature range grade] |
| Development Tool | MAX+PLUS II | — |
| Design Entry | Schematic, VHDL, Verilog HDL, AHDL | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Packaging | Tray | — |
| Logic Architecture | Third-generation MAX (Multiple Array MatriX) | — |
| Fabrication Process | Advanced CMOS | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture | — | Multiple Array MatriX (MAX) - third generation |
| Macro Cells | — | 560 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Propagation Delay (tPD) | — | 20 ns |
| Counter Frequency (fCNT) | — | 100 MHz |
| Supply Voltage (VCC) | — | 5.0 V |
| Process Technology | — | CMOS EEPROM |