EPM9560RI208-20W vs EPM9560RI208-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RI208-20W sa pamamagitan ng Intel at EPM9560RI208-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RI208-20W | EPM9560RI208-10N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | 16 LABs of 40 macrocells each | — |
| User I/O Pins | 212 | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Speed Grade | -20 | — |
| Volte ng Pagbibigay | 5.0 V | 5 V |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Programming Technology | CMOS EEPROM | — |
| Packhaging | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (PQFP) |
| Temperature na Operasyon | -40C to +85C (Industrial) | -40C to +85C (Industrial grade, "RI" suffix) |
| Architecture | Third-generation Multiple Array MatriX (MAX) | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Macro Cells | — | 560 |
| Register Bits | — | 12,160 |
| User I/Os | — | 212 |
| Pin-to-Pin Delay | — | 10 ns (speed grade -10) |
| Maximum Frequency | — | 100 MHz to 125 MHz |
| Programming Method | — | In-system via IEEE 1149.1 (JTAG) |
| Level ng MSL | — | 3 (168 Hours) |
| Tindminan RoHS | — | ROHS3 Compliant (per fpgalink) |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |