EPM9560RI304-15 vs EPM9560RCRC304-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RI304-15 sa pamamagitan ng Intel at EPM9560RCRC304-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RI304-15 | EPM9560RCRC304-15 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Device Family | MAX 9000 | MAX 9000 (EPM9560) |
| Architecture | Multiple Array MatriX (MAX) - EEPROM-based CPLD | Third-generation Multiple Array MatriX (MAX) |
| Macrocells | 560 | — |
| Flip-Flops | 772 | — |
| User I/Os | 212 (216 per some datasheets) | — |
| Dedicated Inputs | 4 | — |
| Total Terminals | 304 | — |
| Package Code | HFQFP / S-PQFP-G304 | — |
| Package Type | 304-pin RQFP (Quad Flat Pack, gull-wing) | — |
| Propagation Delay (tpd) | 11.4 ns (per digchip datasheet); 16.6 ns reported by MicrochipUSA | — |
| Maximum Internal Frequency | 145 MHz | — |
| Speed Grade | -15 | — |
| Supply Voltage (VCCINT/VCCIO) | 4.5 V to 5.5 V (5 V typical) | — |
| I/O Logic Levels | 3.3 V or 5 V configurable | — |
| Temperature na Operasyon | 0 C to 70 C (commercial) | — |
| Temperature Grade | Industrial (per Partstack listings) | — |
| Logic Family | CMOS | — |
| Programming | 5.0-V in-system programmable via JTAG (IEEE 1149.1) | — |
| Process Technology | 0.5 µm CMOS EEPROM | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Logic Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 560 |
| Usable Gates | — | 12,000 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Maximum Frequency | — | 117.6 MHz |
| Volte ng Pagbibigay | — | 5.0 V |
| Configuration Memory | — | EEPROM (non-volatile, in-system programmable) |
| In-System Programmability (ISP) | — | Yes, via IEEE Std. 1149.1 JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 (built-in) |
| Packhaging | — | 304-pin RQFP (PowerQuad Flat Pack) |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |
| Number of User I/O Pins | — | [DATA_NEEDED: user I/O pin count] |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Lead Finish | — | [DATA_NEEDED: lead finish] |