LFE2-6E-5F256I vs LFE2-20E-5F484C Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng LFE2-6E-5F256I sa pamamagitan ng Lattice Semiconductor at LFE2-20E-5F484C sa pamamagitan ng Lattice Semiconductor. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Lattice Semiconductor
LFE2-6E-5F256I - 6K LUT, 190 I/O ECP2 FPGA | Lattice
LFE2-6E-5F256I ✓ Nakahanda
Pagsanggunian na paghahambing
| Parametro | LFE2-6E-5F256I | LFE2-20E-5F484C |
|---|---|---|
| Brand | Lattice Semiconductor | Lattice Semiconductor |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Unknown |
| Device Type | ECP2 Field Programmable Gate Array (FPGA) | ECP2 Field Programmable Gate Array (FPGA) |
| Logic Cells | 6,000 cells | — |
| User I/O | 190 I/O | — |
| Configuration Bits | 56,320 bits | — |
| Core Supply | 1.2 V | — |
| Speed Grade | -5 | -5 |
| Temperature Grade | Industrial | — |
| Packhaging | 256-ball Fine Pitch Ball Grid Array | 484-BBGA |
| Package Abbreviation | FPBGA-256 | — |
| Package Dimensions | 17 mm x 17 mm | — |
| Package Shape | Square | — |
| Terminal Type | Ball | — |
| Terminal Count | 256 balls | 484 balls |
| Uri ng Pagpapasok | Surface mount | Surface Mount |
| Lead-Free Status | Lead free | — |
| Programmable Logic Type | FPGA | — |
| DSP Support | Advanced DSP blocks supported by the LatticeECP2/M family | — |
| SERDES Support | High-speed SERDES supported by the LatticeECP2M family | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| REACH Status | [DATA_NEEDED: REACH status] | [DATA_NEEDED: REACH status] |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification status] | — |
| Logic Cell Density | — | 21K LUTs |
| Input/Output Count | — | 331 I/O |
| Core Supply Voltage | — | 1.2 V |
| DSP Capability | — | DSP |
| Package Type | — | BGA |
| Programmable Device | — | Yes |
| FPGA Family | — | LatticeECP2 |
| Logic Technology | — | 90 nm CMOS |
| Configuration Method | — | [DATA_NEEDED: configuration method] |
| Maksimum na Taktiko ng Oras | — | [DATA_NEEDED: maximum clock frequency] |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |