LTC2150CUJ-14 vs LTC2256CUJ-14 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng LTC2150CUJ-14 sa pamamagitan ng Analog Devices at LTC2256CUJ-14 sa pamamagitan ng Analog Devices. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Analog Devices
LTC2150CUJ-14 - 14-Bit 170Msps 1.8V ADC DDR LVDS | Analog Devices
LTC2150CUJ-14 ✓ NakahandaAnalog Devices
LTC2256CUJ-14 - 14-Bit 25Msps Ultralow Power 1.8V ADC | ADI
LTC2256CUJ-14 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | LTC2150CUJ-14 | LTC2256CUJ-14 |
|---|---|---|
| Brand | Analog Devices | Analog Devices |
| Kategorya | ADC/DAC | ADC/DAC |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Pangangasiwaan | 14 bit | 14 bit |
| Number of Channels | 1 | — |
| Sample Rate | 170 Msps | 25 Msps |
| Architecture | Pipelined | Pipelined |
| Analog Supply Voltage | 1.7 V to 1.9 V (1.8 V nominal) | — |
| Digital Supply Voltage | 1.7 V to 1.9 V (1.8 V nominal) | — |
| INL (typical) | ±0.85 LSB | — |
| DNL (typical) | ±0.25 LSB | — |
| Transition Noise | 1.82 LSBRMS | 1.13 LSB RMS |
| Missing Codes | None over temperature | — |
| Full-Power Sample/Hold Bandwidth | 1.25 GHz | — |
| Digital Output Interface | DDR LVDS | — |
| Encode Clock Inputs | Differential ENC+/ENC- (sine, PECL, LVDS, TTL, CMOS) | — |
| Clock Duty-Cycle Stabilizer | Optional (selectable) | — |
| Configuration Interface | Serial SPI port | Serial SPI port |
| Latency | 5 clock cycles | — |
| Power-Saving Modes | Sleep and Nap modes | Nap mode, full shutdown |
| Packhaging | 40-QFN (6 mm × 6 mm) with exposed pad | 40-QFN (6 mm x 6 mm) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Compliant (Pb-free #PBF suffix) | Compliant (PBF suffix) |
| Number of Inputs | — | 1 |
| Volte ng Pagbibigay | — | 1.8 V (single) |
| Power Dissipation | — | 35 mW at 25 Msps |
| INL | — | ±1 LSB (typical) |
| DNL | — | ±0.3 LSB (typical) |
| SNR | — | 73 dB |
| Input Bandwidth (Full Power) | — | 800 MHz |
| Input Range | — | 1 Vp-p to 2 Vp-p (selectable, differential) |
| Digital Output Modes | — | Full-rate CMOS, DDR CMOS, DDR LVDS (selectable) |
| Output Supply Range (CMOS) | — | 1.2 V to 1.8 V |
| Pin/Package Code | — | UJ (QFN-40, 6x6 mm) |
| Optional Features | — | Clock duty-cycle stabilizer, data output randomizer |
| Temperature na Operasyon | — | 0C to +70C (commercial C-grade) |