LTC2257CUJ-14 vs LTC2150CUJ-14 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng LTC2257CUJ-14 sa pamamagitan ng Analog Devices at LTC2150CUJ-14 sa pamamagitan ng Analog Devices. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Analog Devices
LTC2257CUJ-14 - 14-Bit 40Msps Ultralow Power ADC | Analog Devices
LTC2257CUJ-14 ✓ NakahandaAnalog Devices
LTC2150CUJ-14 - 14-Bit 170Msps 1.8V ADC DDR LVDS | Analog Devices
LTC2150CUJ-14 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | LTC2257CUJ-14 | LTC2150CUJ-14 |
|---|---|---|
| Brand | Analog Devices | Analog Devices |
| Kategorya | ADC/DAC | ADC/DAC |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Pangangasiwaan | 14 bit | 14 bit |
| Sample Rate | 40 Msps | 170 Msps |
| Architecture | Pipelined | Pipelined |
| Number of Inputs | 1 | — |
| Supply Voltage (Analog) | 1.8 V (typ) | — |
| Power Dissipation | 49 mW at 40 Msps | — |
| Input Range (selectable) | 1 Vp-p to 2 Vp-p | — |
| Full-Power Input Bandwidth | 800 MHz | — |
| INL (typical) | ±1 LSB | ±0.85 LSB |
| DNL (typical) | ±0.3 LSB | ±0.25 LSB |
| Transition Noise | 1.13 LSB RMS | 1.82 LSBRMS |
| Missing Codes Over Temperature | None | — |
| Digital Outputs | Full-rate CMOS / DDR CMOS / DDR LVDS (selectable) | — |
| Output Supply Range (OVDD) | 1.2 V to 1.8 V | — |
| Configuration Interface | Serial SPI port | Serial SPI port |
| Power-Saving Modes | Shutdown and Nap | Sleep and Nap modes |
| Optional Features | Data output randomizer, clock duty cycle stabilizer | — |
| Packhaging | 40-pin QFN (6 mm × 6 mm) | 40-QFN (6 mm × 6 mm) with exposed pad |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Compliance | RoHS compliant (Pb-free #PBF suffix) | — |
| Number of Channels | — | 1 |
| Analog Supply Voltage | — | 1.7 V to 1.9 V (1.8 V nominal) |
| Digital Supply Voltage | — | 1.7 V to 1.9 V (1.8 V nominal) |
| Missing Codes | — | None over temperature |
| Full-Power Sample/Hold Bandwidth | — | 1.25 GHz |
| Digital Output Interface | — | DDR LVDS |
| Encode Clock Inputs | — | Differential ENC+/ENC- (sine, PECL, LVDS, TTL, CMOS) |
| Clock Duty-Cycle Stabilizer | — | Optional (selectable) |
| Latency | — | 5 clock cycles |
| Tindminan RoHS | — | Compliant (Pb-free #PBF suffix) |