MPC8536EAVTATHA vs MPC8536EAVTATHA557 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng MPC8536EAVTATHA sa pamamagitan ng NXP Semiconductors at MPC8536EAVTATHA557 sa pamamagitan ng NXP Semiconductors. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
NXP Semiconductors
MPC8536EAVTATHA - PowerQUICC III 1.25GHz 32-Bit MPU | NXP
MPC8536EAVTATHA ✓ NakahandaNXP Semiconductors
MPC8536EAVTATHA557 - PowerQUICC III 1.25GHz e500 MPU | NXP
MPC8536EAVTATHA557 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | MPC8536EAVTATHA | MPC8536EAVTATHA557 |
|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors |
| Kategorya | Microcontrollers | DSP |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Manufacturer | NXP Semiconductors (formerly Freescale) | — |
| Processor Type | MPC85xx PowerQUICC III, 32-Bit PowerPC e500 | PowerPC e500 Microprocessor IC MPC85xx |
| Core Count | 1 | — |
| Core Frequency | 1.25 GHz | 1.25 GHz |
| Core Architecture | PowerPC e500, superscalar | PowerPC e500 (32-bit, dual-issue superscalar) |
| Operating Voltage (Core) | 1 V | 1.0 V |
| I/O Voltage | 1.5V / 1.8V / 2.5V / 3.3V | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Memory Controller | DDR2 / DDR3 with ECC | DDR2 / DDR3 with ECC support |
| Ethernet | 2x Gigabit (SGMII) | — |
| SATA | 2x SATA (multiplexed with SGMII) | — |
| PCI / PCIe | PCI and PCIe interfaces | — |
| Storage I/O | SD / MMC (SDHC) | — |
| Security Engine | SEC 4.0 (AES, 3DES, hashing, RNG) | DES / 3DES / AES / Public-key acceleration |
| Hardware Timestamping | IEEE 1588 | — |
| Packhaging / Kaso | 783-FCPBGA (29x29 mm) | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Temperature na Operasyon | 0C to +90C | -40C to +105C |
| Tindminan RoHS | Compliant | Compliant |
| Number of Cores | — | 1 |
| Packhaging | — | 783-FCPBGA (29x29 mm) |
| Ethernet Controllers | — | 4 x 10/100/1000 Mbps eTSEC |
| PCI Express Lanes | — | PCIe Gen 2 x4 |
| Lead-Free Status | — | Lead-Free [DATA_NEEDED: reflow profile] |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| JTAG Support | — | JTAG / COP / BDI debug interface |
| L1 Cache | — | 32 KB instruction + 32 KB data |