MPC8548EVTAVHD557 vs MPC8548EVTAVHD Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng MPC8548EVTAVHD557 sa pamamagitan ng NXP Semiconductors at MPC8548EVTAVHD sa pamamagitan ng NXP Semiconductors. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | MPC8548EVTAVHD557 | MPC8548EVTAVHD |
|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors |
| Kategorya | Microcontrollers | Microcontrollers |
| Katayuan ng Lifecycle | NRND | Aktibo |
| Family | PowerQUICC III (MPC85xx) | — |
| Core | Power Architecture e500, 32-bit | — |
| Core Frequency | 1.5 GHz | — |
| Instruction Set | Power Architecture Book E + signal-processing engine | — |
| FPU | Double-precision hardware FPU | — |
| L1 Cache | 32 KB instruction + 32 KB data | 32 KB I-cache + 32 KB D-cache |
| L2 Cache | [DATA_NEEDED: L2 cache size] | 512 KB unified on-chip |
| Security Engine | SEC 2.0 (IPsec, SSL/TLS, 3DES, AES, SHA, RSA, ECC) | SEC 2.0 (AES, DES, 3DES, Kasumi, SHA, MD5, public-key) |
| Gigabit Ethernet | 3x 10/100/1000 enhanced GETH with SGMII / RGMII / RTBI | — |
| PCI Express | 2x PCIe interfaces (x1/x2/x4 capable) | 2x PCIe interfaces |
| Serial RapidIO | 2x SRIO ports (1x/4x lane) | 2x SRIO ports |
| DDR Memory Controller | 2x 64-bit DDR2 with ECC, up to 533 MHz | — |
| PCI / PCI-X | 2x 64-bit PCI / PCI-X controllers | 2x 64-bit PCI/PCI-X |
| Local Bus | 8-bit / 16-bit / 32-bit Local Bus + GPIO | — |
| Serial I/O | 4x I2C, 2x UART, DUART, SPI | — |
| Temperature na Operasyon | 0 C to +105 C (extended) | 0C to +105C |
| Volte ng Pagbibigay | 1.0 V core / 1.5 V DDR / 1.8 V / 2.5 V / 3.3 V I/O | — |
| Packhaging | 783-ball FCBGA, 29x29 mm | 783-FCBGA (29x29 mm) |
| Process Node | 90 nm CMOS | — |
| Tindminan RoHS | Compliant (lead-free FCBGA) | [DATA_NEEDED: rohs status] |
| Series | — | PowerQUICC III |
| Core Architecture | — | Power Architecture e500 v2 |
| Core Count | — | 1 |
| Bit Width | — | 32-bit |
| Maximum CPU Clock | — | 1.5 GHz |
| Process Technology | — | 0.09 um CMOS |
| Memory Controller | — | 64-bit DDR2 SDRAM with ECC, up to 533 MT/s |
| Ethernet | — | 4x Gigabit Ethernet (SGMII/RGMII/TBI/RTBI) |
| Supply Voltage na Operasyon | — | 1.8 V / 2.5 V / 3.3 V |
| Uri ng Pagpapasok | — | Surface Mount |
| Silicon Revision | — | R3 |