P5010NXE1QMB557 vs P5010NXE1QMB Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng P5010NXE1QMB557 sa pamamagitan ng NXP Semiconductors at P5010NXE1QMB sa pamamagitan ng NXP Semiconductors. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
NXP Semiconductors
P5010NXE1QMB557 - QorIQ P5010 e5500 SoC 1.6GHz FC-PBGA-1295 | NXP
P5010NXE1QMB557 ✓ NakahandaNXP Semiconductors
P5010NXE1QMB - QorIQ P5 1.6GHz e5500 SoC | NXP | Networking
P5010NXE1QMB ✓ NakahandaPagsanggunian na paghahambing
| Parametro | P5010NXE1QMB557 | P5010NXE1QMB |
|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors |
| Kategorya | Microcontrollers | Microcontrollers |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | QorIQ P5 | QorIQ P5 |
| Core Architecture | Power Architecture e5500, 64-bit | — |
| Number of Cores | 1 | — |
| Maximum Core Frequency | 1.6 GHz (1600 MHz) | — |
| Secondary Core Frequency | 1.2 GHz (1200 MHz, r2.0) | — |
| L1 I-Cache per Core | 32 KB | — |
| L1 D-Cache per Core | 32 KB | — |
| Memory Controller | DDR3/DDR3L with ECC | DDR3 / DDR3L with ECC up to 1.33 GT/s |
| PCIe Lanes | Yes | — |
| Serial RapidIO (SRIO) | Yes | — |
| Gigabit Ethernet | Yes (multiple SerDes lanes) | — |
| Security Engine (SEC) | Integrated | — |
| Hardware Acceleration | Integrated | — |
| Temperature na Operasyon | -40C to +105C (extended) | -40C to +105C (extended, NX suffix) |
| Packhaging | 1295-ball FC-PBGA (37.5x37.5 mm) | 1295-FCPBGA, 37.5x37.5 mm, 1.00 mm pitch |
| Ball Pitch | 1.00 mm | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Boundary Scan | Yes (IEEE 1149.1/JTAG) | — |
| Architecture | — | Power Architecture e5500, 64-bit |
| Core Count | — | 1 (single core) |
| CPU Frequency (nominal) | — | 1.6 GHz |
| CPU Frequency (turbo) | — | 2.0 GHz |
| L2 Cache | — | 512 KB per core |
| Ethernet | — | Gigabit Ethernet (multiple MACs) |
| PCIe | — | PCI Express Gen2 (multiple lanes) |
| Serial RapidIO | — | 2x SRIO ports |
| Security Engine | — | SEC 4.x (E1 suffix enabled) |
| HW Acceleration | — | Pattern matching engine for packet classification |
| Core Voltage | — | 1.1 V |
| Process | — | 45 nm CMOS |
| Tindminan RoHS | — | Compliant |