RTAX250SL-1CG624E vs RTAX250SL-1LG624V Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng RTAX250SL-1CG624E sa pamamagitan ng Microchip Technology at RTAX250SL-1LG624V sa pamamagitan ng Microchip Technology. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Microchip Technology
RTAX250SL-1CG624E - 250K Gate Rad-Tolerant FPGA, CCGA-624 | Microchip
RTAX250SL-1CG624E ✓ NakahandaMicrochip Technology
RTAX250SL-1LG624V - 250K-Gate Rad-Tolerant FPGA | Microchip
RTAX250SL-1LG624V ✓ NakahandaPagsanggunian na paghahambing
| Parametro | RTAX250SL-1CG624E | RTAX250SL-1LG624V |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Equivalent System Gates | 250,000 gates | 250,000 gates |
| Configurable Logic Blocks (CLBs) | 2816 | 2816 |
| Logic Cells | 4224 | 4224 |
| User I/O | 248 inputs / 248 outputs | — |
| Core Supply Voltage | 1.5 V (1.425 V to 1.575 V) | 1.5 V nominal |
| Maximum Combinatorial Delay (CLB) | 0.93 ns | — |
| Maximum System Frequency | 649 MHz | — |
| Process Technology | 0.15 um CMOS | — |
| Logic Family | CMOS | — |
| Packhaging | 624-ball Ceramic Column Grid Array (CCGA-624) | 624-terminal ceramic CGA (LG624), 1.270 mm terminal pitch |
| Temperature na Operasyon | -55C to +125C | -55C to +125C |
| Radiation Tolerance | SEU-immune to specified LET threshold; SEU rate < 10-10 errors/bit-day | — |
| SEU Mitigation | SEU-hardened registers (no external TMR required) | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| Configuration | Live-at-power-up, true single-chip operation | — |
| Uri ng Pagpapasok | Surface Mount (ceramic column grid array) | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| I/O Supply Voltage | [DATA_NEEDED: I/O bank voltage] | — |
| Architecture | — | CMOS antifuse (Axcelerator-derived) |
| Family | — | RTAX-S/SL Radiation-Tolerant FPGA |
| Speed Grade | — | -1 |
| Configuration Type | — | One-Time Programmable (antifuse) |
| Clock Resources | — | Segmentable clocks, chip-wide highway routing |
| Arithmetic Support | — | Dedicated carry logic |
| Application Domain | — | Space-flight systems |
| Total Ionizing Dose Tolerance | — | [DATA_NEEDED: TID level] |