XC6SLX45-2FGG484I vs XC6SLX45-2FGG676I Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng XC6SLX45-2FGG484I sa pamamagitan ng AMD at XC6SLX45-2FGG676I sa pamamagitan ng AMD. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | XC6SLX45-2FGG484I | XC6SLX45-2FGG676I |
|---|---|---|
| Brand | AMD | AMD |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Spartan-6 LX | Spartan-6 LX |
| Logic Cells | 43,661 | 43,661 |
| Logic Slices | 6,822 | — |
| Flip-Flops | 54,576 | — |
| Block RAM | 2,138,112 bits (2,088 Kb/s) | 2,088 Kbit |
| DSP Slices (DSP48A1) | 58 | — |
| Maximum User I/O | 316 | — |
| Packhaging | 484-ball BGA (FBGA-484) | 676-ball FBGA (FGG676), 27 x 27 mm, 1.0 mm pitch |
| Package Dimensions | 23 x 23 mm, 1.0 mm ball pitch | — |
| Speed Grade | -2 | -2 |
| Operating Temperature (I grade) | -40C to +100C (industrial) | — |
| Process Technology | 45 nm low-power CMOS | 45 nm CMOS |
| Supply Voltage Core | 1.2 V typical | — |
| Clock Management Tiles | 6 CMT (4 DCM + 2 PLL) | — |
| Maximum I/O Speed | 800 Mbps LVDS | — |
| Memory Interface Support | DDR, DDR2, DDR3, LPDDR | — |
| Configuration Memory | AES-256 bitstream encryption | — |
| RoHS Compliance | Lead-free / RoHS compliant | — |
| Part Number | — | XC6SLX45-2FGG676I |
| Configurable Logic Blocks (CLBs) | — | 3,411 |
| Total Flip-Flops | — | 54,576 |
| DSP48A1 Slices | — | 58 |
| User I/Os | — | 358 |
| Number of I/O Banks | — | 4 |
| Core Voltage | — | 1.2 V |
| Internal Frequency | — | 500 MHz |
| Operating Temperature (Industrial) | — | -40 °C to +100 °C |
| Compliance | — | RoHS compliant, Lead Free |