5CSEBA5U19I7SN vs 5CSEBA4U19I7SN Karşılaştırma

Ayrıntılı yan yana karşılaştırma 5CSEBA5U19I7SN tarafından Altera ve 5CSEBA4U19I7SN tarafından IntelAnahtar özellikleri, elektriksel parametreleri, ambalajı, yaşam döngüsü durumu, fiyatlandırma ve mevcudiyeti karşılaştırarak tasarım gereksinimleriniz için en iyi bileşeni belirleyin.

Özellik Karşılaştırması

Parametre 5CSEBA5U19I7SN 5CSEBA4U19I7SN
Marka Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Yaşam Döngüsü Durumu Aktif Aktif
Family Cyclone V SE SoC FPGA —
Device Variant 5CSEA5 —
Logic Elements 85K 40,000
Hard Processor System Single-core ARM Cortex-A9 MPCore with CoreSight —
HPS Maximum Clock 800 MHz —
FPGA Fabric Maximum Clock [DATA_NEEDED: maximum fabric frequency] —
Paket 484-pin UBG (Ultra FineLine BGA, 19x19 mm) 484-pin UBG A (19x19 mm)
Package Designator U19 —
Speed/Logic Grade A5 (mid-tier speed grade) —
User I/O Count 66 (per distributor listing); up to 288 in Cyclone V SE family typical —
Embedded Memory [DATA_NEEDED: total Kbits] [DATA_NEEDED: total Kbits of M9K blocks]
DSP Blocks [DATA_NEEDED: DSP block count for 5CSEA5] —
PLL Count [DATA_NEEDED: PLL count for 5CSEA5] —
Transceivers [DATA_NEEDED: transceiver count for 5CSEA5 U19] Not applicable (SE family, transceiver-less)
İşletim Jant Sıcaklığı -40C to +100C (industrial) —
Process Technology TSMC 28 nm low-power —
Configuration SRAM-based, volatile —
Montaj Türü Surface Mount (BGA) Surface Mount
RoHS Durumu Compliant Compliant
MSL Seviyesi [DATA_NEEDED: moisture sensitivity level] —
Series — Cyclone V SE SoC FPGA
Device Family — Cyclone V
Hard Processor System (HPS) — Single ARM Cortex-A9 MPCore with CoreSight
HPS Maximum Frequency — 800 MHz
İşletim Sıcaklığı — -40C to +100C (Industrial)
Process Node — 28 nm low-power
Supply Voltage (Core) — 1.1 V (typical)
I/O Standards Supported — LVTTL, LVCMOS, LVDS, SSTL, HSTL (Cyclone V I/O family)
18x18 Hardware Multipliers — [DATA_NEEDED: count]
PLLs — [DATA_NEEDED: count]
PCI Express Hard IP — Gen1 capable (rootport/endpoint)
DDR Memory Support — DDR2/DDR3/LPDDR2 via HPS and FPGA fabric

Dökümanlar & Kaynaklar

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