EP610ILC10 vs EP610IDC-15 Karşılaştırma
Ayrıntılı yan yana karşılaştırma EP610ILC10 tarafından Intel ve EP610IDC-15 tarafından IntelAnahtar özellikleri, elektriksel parametreleri, ambalajı, yaşam döngüsü durumu, fiyatlandırma ve mevcudiyeti karşılaştırarak tasarım gereksinimleriniz için en iyi bileşeni belirleyin.
Özellik Karşılaştırması
| Parametre | EP610ILC10 | EP610IDC-15 |
|---|---|---|
| Marka | Intel | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Yaşam Döngüsü Durumu | NRND | Son Alış Zamanı |
| Family | Classic EPLD (EP610) | — |
| Logic Elements | 16 macrocells | — |
| Gates | 300 gates equivalent | — |
| Product Terms | 160 | — |
| I/O Lines | 16 | — |
| Dedicated Inputs | 4 | — |
| Propagation Delay (tPD) | 15 ns (10 ns speed grade) | 15 ns |
| Maximum Internal Frequency | 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| İşletim Sıcaklığı | -40 C to +85 C (Industrial) | 0C to +70C (commercial) |
| Technology | CMOS, UV-erasable / OTP | — |
| Architecture | PAL-type AND-OR-NOT | — |
| Paket | 28-pin PLCC (J-Lead) | 24-pin CerDIP (ceramic DIP) |
| Montaj Türü | Surface Mount / Socket | Through-hole |
| RoHS Durumu | Unknown - verify with manufacturer | [DATA_NEEDED: RoHS status of CerDIP variant] |
| Device Family | — | Altera Classic EPLD |
| Macrocells | — | 16 |
| Usable Gates | — | 300 |
| Maximum Frequency | — | 66 MHz |
| Process Technology | — | CMOS, UV-erasable / OTP |
| I/O Pins | — | 24 (per package; macrocell-programmable) |
| Logic-Block Architecture | — | AND/OR macrocell array with programmable flip-flops |
| Program/Erase | — | UV-erasable, OTP-compatible |
| Development Tool | — | MAX+PLUS II |
| Programming Current | — | 11.0 mA typical (per Classic family datasheet) |