EPC2LC20V vs EPC2LC20 Karşılaştırma

Ayrıntılı yan yana karşılaştırma EPC2LC20V tarafından Intel ve EPC2LC20 tarafından AlteraAnahtar özellikleri, elektriksel parametreleri, ambalajı, yaşam döngüsü durumu, fiyatlandırma ve mevcudiyeti karşılaştırarak tasarım gereksinimleriniz için en iyi bileşeni belirleyin.

Özellik Karşılaştırması

Parametre EPC2LC20V EPC2LC20
Marka Intel Altera
Kategori FPGA & CPLD Memory ICs
Yaşam Döngüsü Durumu NRND NRND
Birim Fiyat (USD) — $7,20
Product Type Flash Configuration Device (FPGA configuration PROM) —
Bellek Boyutu 1.6 Mb (1,678,336 bits) 1.6 Mbit
Configuration Interface Serial (Passive Serial) or 8-bit parallel Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE
Maximum Configuration Clock 10 MHz —
Operating Voltage (VCC) 3.0 V to 3.6 V (3.3 V typ.) —
Program/Erase Cycles 100,000 cycles minimum —
Data Retention 20 years minimum —
JTAG Support IEEE 1149.1 Boundary Scan, in-system programmable —
Paket PLCC-20 (JEDEC MO-047) 20-pin PLCC (J-lead, 9x9 mm)
İşletim Sıcaklığı -40C to +85C (industrial) -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet]
Storage Temperature -65C to +150C —
Lead-Free / RoHS Lead-free (V suffix), RoHS compliant —
Compatible FPGAs Cyclone, Stratix, APEX 20K, ACEX 1K, FLEX 10K, FLEX 8000 —
On-chip Oscillator Yes (generates DCLK) —
Configuration Time (typical) Depends on FPGA bitstream length and clock mode —
MSL Seviyesi [DATA_NEEDED: MSL level] —
Bellek Türü — Non-volatile configuration PROM
Programming Interface — IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant
Supply Voltage VCC — 3.0 V to 3.6 V (3.3-V operation)
ISP Voltage Range — 5.0 V or 3.3 V
Supported FPGA Families — ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000
Cascade Support — Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams
Montaj Türü — Surface Mount
RoHS Durumu — Non-Compliant (original Altera Pb-containing part)
Lead-Free Version — EPC2LC20N available as lead-free equivalent
Programming Support — Altera Programming Unit (APU), Quartus II, JTAG programmer
Boundary-Scan — IEEE 1149.1 compliant, 8-bit or 16-bit JTAG

Dökümanlar & Kaynaklar

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