EPM3512AFC256-20 vs EPM3512AFC256-10N Karşılaştırma
Ayrıntılı yan yana karşılaştırma EPM3512AFC256-20 tarafından Altera ve EPM3512AFC256-10N tarafından AlteraAnahtar özellikleri, elektriksel parametreleri, ambalajı, yaşam döngüsü durumu, fiyatlandırma ve mevcudiyeti karşılaştırarak tasarım gereksinimleriniz için en iyi bileşeni belirleyin.
Altera
EPM3512AFC256-20 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-20 Obsolete
Özellik Karşılaştırması
| Parametre | EPM3512AFC256-20 | EPM3512AFC256-10N |
|---|---|---|
| Marka | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Yaşam Döngüsü Durumu | Obsolete | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Typical Usable Gates | 10,000 | — |
| Speed Grade | -20 (20 ns tPD) | — |
| Paket | 256-ball FBGA (Fine-pitch BGA) | 256-ball FBGA (17 mm x 17 mm) |
| Pin Sayısı | 256 | — |
| Operating Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | — |
| I/O Voltage (VCCIO) | 2.5 V or 3.3 V (5.0 V tolerant inputs) | — |
| I/O Standards | LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant | — |
| Program Memory Type | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | — |
| JTAG Support | Yes (boundary-scan + ISP) | — |
| Montaj Türü | Surface Mount | Surface Mount (BGA) |
| İşletim Sıcaklığı | [DATA_NEEDED: operating temperature range] | — |
| RoHS Durumu | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| MSL Seviyesi | [DATA_NEEDED: MSL moisture sensitivity level] | [DATA_NEEDED: MSL rating] |
| Configuration Memory | Internal EEPROM | — |
| Usable Gates | — | 10000 |
| User I/O Pins | — | 208 |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: number of LABs] |
| Operating Frequency (fMAX) | — | [DATA_NEEDED: fMAX MHz] |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Setup Time (tSU) | — | 4.5 ns |
| VCCINT (Core Supply) | — | 3.3 V |
| VCCIO (I/O Supply) | — | 3.3 V or 2.5 V |
| Technology | — | CMOS EEPROM-based, non-volatile |
| Operating Temperature (Commercial) | — | 0 C to +70 C |
| ISP Interface | — | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |