EPM3512AQC208-15N vs EPM3512AQC208-10-10N Karşılaştırma
Ayrıntılı yan yana karşılaştırma EPM3512AQC208-15N tarafından Altera ve EPM3512AQC208-10-10N tarafından AlteraAnahtar özellikleri, elektriksel parametreleri, ambalajı, yaşam döngüsü durumu, fiyatlandırma ve mevcudiyeti karşılaştırarak tasarım gereksinimleriniz için en iyi bileşeni belirleyin.
Altera
EPM3512AQC208-15N - 512-Macro CPLD MAX 3000A PQFP-208 | Altera
EPM3512AQC208-15N ⚠ Son Satın AlmaAltera
EPM3512AQC208-10-10N - MAX 3000A CPLD 512 Macrocells 208-PQFP | Altera
EPM3512AQC208-10-10N ObsoleteÖzellik Karşılaştırması
| Parametre | EPM3512AQC208-15N | EPM3512AQC208-10-10N |
|---|---|---|
| Marka | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Yaşam Döngüsü Durumu | Son Alış Zamanı | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Macro Cells | 512 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 172 | — |
| Typical Usable Gates | 12,000 | — |
| Number of Logic Elements | 512 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Operating Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V (MultiVolt) | 2.5 V / 3.3 V / 5.0 V |
| Programmable I/O Standards | LVTTL, LVCMOS, PCI (with external resistor) | — |
| In-System Programmability | Yes (IEEE Std. 1532 compliant) | Yes, IEEE Std. 1532 compliant |
| Configuration Memory | EEPROM (non-volatile) | — |
| JTAG Support | Yes (BST/Boundary-Scan Test) | — |
| Paket | PQFP-208 (QC208) | 208-pin PQFP (Plastic Quad Flat Pack) |
| Montaj Türü | Surface Mount | Surface Mount |
| İşletim Sıcaklığı | 0C to +70C (commercial) | 0 °C to +70 °C (commercial) |
| RoHS Durumu | [DATA_NEEDED: RoHS status] | — |
| Macrocells | — | 512 |
| Usable Gates | — | 10,000 |
| User I/Os | — | 172 |
| Logic Elements / LABs | — | 16 Logic Array Blocks |
| Propagation Delay (tPD) | — | 10 ns (-10 speed grade) |
| Maximum Frequency (fCNT) | — | 87 MHz |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| Process Technology | — | CMOS EEPROM |
| Boundary-Scan (JTAG) | — | Yes, IEEE 1149.1 |
| PCI-SIG Compliance | — | PCI Local Bus Specification Rev 2.2 (at -10 speed grade) |
| Lead-Free / RoHS | — | [DATA_NEEDED: RoHS status] |