RTAX250SL-1CG624B vs RTAX250SL-1CG624E Karşılaştırma
Ayrıntılı yan yana karşılaştırma RTAX250SL-1CG624B tarafından Microchip Technology ve RTAX250SL-1CG624E tarafından Microchip TechnologyAnahtar özellikleri, elektriksel parametreleri, ambalajı, yaşam döngüsü durumu, fiyatlandırma ve mevcudiyeti karşılaştırarak tasarım gereksinimleriniz için en iyi bileşeni belirleyin.
Microchip Technology
RTAX250SL-1CG624B - 250K-Gate Rad-Tolerant FPGA | Microchip
RTAX250SL-1CG624B ✓ AktifMicrochip Technology
RTAX250SL-1CG624E - 250K Gate Rad-Tolerant FPGA, CCGA-624 | Microchip
RTAX250SL-1CG624E ✓ AktifÖzellik Karşılaştırması
| Parametre | RTAX250SL-1CG624B | RTAX250SL-1CG624E |
|---|---|---|
| Marka | Microchip Technology | Microchip Technology |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Yaşam Döngüsü Durumu | Aktif | Aktif |
| Family | RTAX-SL (RTAX-S/SL RadTolerant FPGAs) | — |
| Equivalent System Gates | 250000 gates | 250,000 gates |
| Logic Cells (CLBs) | 2816 CLBs | — |
| Azami Saat Hızı | 649 MHz | — |
| CLB Combinatorial Delay (Max) | 0.930 ns | — |
| Process Technology | 0.15 um | 0.15 um CMOS |
| Core Supply Voltage | 1.5 V | 1.5 V (1.425 V to 1.575 V) |
| Paket | 624-Pin CCGA (Ceramic Column Grid Array) | 624-ball Ceramic Column Grid Array (CCGA-624) |
| Speed Grade | -1 | — |
| Ordering Format | Box | — |
| Programming Technology | Antifuse (one-time programmable, live-at-power-up) | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| İşletim Sıcaklığı | [DATA_NEEDED: Operating Temperature Range] | -55C to +125C |
| Maximum I/O Count | [DATA_NEEDED: I/O count for CG624 package] | — |
| Total Ionizing Dose (TID) Tolerance | [DATA_NEEDED: TID rating] | — |
| Montaj Türü | Surface Mount | Surface Mount (ceramic column grid array) |
| RoHS Durumu | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Configurable Logic Blocks (CLBs) | — | 2816 |
| Logic Cells | — | 4224 |
| User I/O | — | 248 inputs / 248 outputs |
| Maximum Combinatorial Delay (CLB) | — | 0.93 ns |
| Maximum System Frequency | — | 649 MHz |
| Logic Family | — | CMOS |
| Radiation Tolerance | — | SEU-immune to specified LET threshold; SEU rate < 10-10 errors/bit-day |
| SEU Mitigation | — | SEU-hardened registers (no external TMR required) |
| Configuration | — | Live-at-power-up, true single-chip operation |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O bank voltage] |