EP610PC-30 vs EP610PC-25T موازنہ
تفصیلی ساتھ ساتھ موازنہ از EP610PC-30 بذریعہ Altera اور EP610PC-25T بذریعہ Intel. اہم خصوصیات، برقی پیرامیٹرز، پیکیجنگ، لائف سائیکل اسٹیٹس، قیمتوں اور دستیابی کا موازنہ کریں تاکہ آپ کی ڈیزائن ضروریات کے لیے بہترین کمپوننٹ کا تعین ہو سکے۔
Intel
EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
EP610PC-25T ⚠ آخری بار خریداریخصوصیات کا موازنہ
| پیرامیٹر | EP610PC-30 | EP610PC-25T |
|---|---|---|
| برانڈ | Altera | Intel |
| زمرہ | FPGA & CPLD | FPGA & CPLD |
| لائف سائیکل کی حالت | NRND | آخری بار خریداری |
| Device Family | Classic EPLD (EP610) | Altera Classic EPLD - EP610 |
| Macrocells | 16 | — |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 30 ns | 25 ns (speed grade 25) |
| Maximum Pipeline Frequency | 33.3 MHz (typical) / 100 MHz pipelined | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V |
| Process Technology | CMOS EPROM | ECMOS (CMOS, EPROM-based) |
| پیکیج | 24-pin PDIP (0.300 inch) | PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) |
| ماؤنٹنگ ٹائپ | Through-Hole | Through-hole |
| Programmability | One-Time Programmable (OTP, no window on plastic PDIP) | — |
| آپریٹنگ درجہ حرارت | 0C to +70C (commercial) | 0 °C to +70 °C (commercial) |
| Output Drive Current | [DATA_NEEDED: IOH/IOL per datasheet DC characteristics] | — |
| Input Pins (Dedicated) | [DATA_NEEDED: dedicated input count from datasheet pinout] | — |
| I/O Pins | [DATA_NEEDED: bidirectional I/O count from datasheet pinout] | — |
| Programming Tool | Altera A+PLUS / MAX+PLUS II (legacy) | — |
| RoHS اسٹیٹس | Not applicable (legacy non-compliant package per distributor listing) | [DATA_NEEDED: RoHS status] |
| Lead Free Status | Not applicable | — |
| Current Distributor | Rochester Electronics, LLC (authorized continuing source) | — |
| Manufacturer | — | Intel (formerly Altera) |
| Distributor / Stocking Source | — | Rochester Electronics, LLC |
| Device Type | — | Erasable Programmable Logic Device (EPLD, OTP for plastic package) |
| Logic Capacity | — | 300 usable gates |
| Macro Cells | — | 16 |
| Registers | — | 16 |
| User I/Os | — | 16 |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fmax] |
| Pipelined Data Rate | — | up to 100 MHz |
| Pinout Compatibility | — | Pin-compatible with EP610DC-25 (CERDIP-24, windowed) |
| Programming Method | — | OTP (one-time programmable) via Altera programming hardware |
| Shipping Form (T suffix) | — | Tube |