EP610PC-30 vs EP610PC-25T 比較

詳細並排比較 EP610PC-30 由 Altera 與 EP610PC-25T 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP610PC-30 EP610PC-25T
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND 最後購買
Device Family Classic EPLD (EP610) Altera Classic EPLD - EP610
Macrocells 16 —
Usable Gates 300 —
Propagation Delay (tPD) 30 ns 25 ns (speed grade 25)
Maximum Pipeline Frequency 33.3 MHz (typical) / 100 MHz pipelined —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) 5 V
Process Technology CMOS EPROM ECMOS (CMOS, EPROM-based)
封裝 24-pin PDIP (0.300 inch) PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing)
安裝類型 Through-Hole Through-hole
Programmability One-Time Programmable (OTP, no window on plastic PDIP) —
工作溫度 0C to +70C (commercial) 0 °C to +70 °C (commercial)
Output Drive Current [DATA_NEEDED: IOH/IOL per datasheet DC characteristics] —
Input Pins (Dedicated) [DATA_NEEDED: dedicated input count from datasheet pinout] —
I/O Pins [DATA_NEEDED: bidirectional I/O count from datasheet pinout] —
Programming Tool Altera A+PLUS / MAX+PLUS II (legacy) —
RoHS 狀態 Not applicable (legacy non-compliant package per distributor listing) [DATA_NEEDED: RoHS status]
Lead Free Status Not applicable —
Current Distributor Rochester Electronics, LLC (authorized continuing source) —
Manufacturer — Intel (formerly Altera)
Distributor / Stocking Source — Rochester Electronics, LLC
Device Type — Erasable Programmable Logic Device (EPLD, OTP for plastic package)
Logic Capacity — 300 usable gates
Macro Cells — 16
Registers — 16
User I/Os — 16
Maximum Toggle Frequency — [DATA_NEEDED: max fmax]
Pipelined Data Rate — up to 100 MHz
Pinout Compatibility — Pin-compatible with EP610DC-25 (CERDIP-24, windowed)
Programming Method — OTP (one-time programmable) via Altera programming hardware
Shipping Form (T suffix) — Tube

資料表與資源

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