EP910PI-35 - 24-Macrocell Classic EPLD, 35ns, PDIP-40 | Rochester/Altera
MPN: EP910PI-35 ✓ فعالEP910PI-35 جائزہ
A Programmable Logic Device (PLD) is a digital integrated circuit whose logic function is defined by the customer after manufacture, allowing a single part to replace many discrete TTL/CMOS glue-logic ICs. EPLDs specifically use EPROM (UV-erasable) technology and sit in the programmable-logic hierarchy below modern CPLDs and FPGAs; the Classic EPLD family was Altera's first-generation product line and remains a building block in legacy industrial, telecom, and military designs where pin-compatible continuity is required.
Key features include 24 macrocells organized as 12 dedicated inputs and 24 I/O pins (bidirectional), 450 usable gates, 35 ns tPD (propagation delay), 28.6 MHz fMAX, and 5 V CMOS I/O. The device is in-circuit programmable via a standard Altera programming hardware, and the ceramic windowed version allows erasure with UV light for re-use. The EP910 family predates JTAG and uses the legacy Altera programming interface. The PDIP-40 package gives the part a robust through-hole footprint suited to prototyping, MIL-spec assemblies, and long-lifecycle industrial control boards.
Typical applications include address decoding and bus-interface glue logic in legacy 80C186/68k systems, control logic in industrial PLCs, state-machine replacement of TTL MSI, custom peripheral decoders in VME/cPCI backplanes, and avionics/military systems where the EP910 has been qualified for decades. Rochester Electronics' authorized stock ensures long-term availability for EOL-prone designs.
When designing with this device, ensure the programming algorithm matches the EP910 family (legacy Altera software such as MAX+PLUS II is required), respect the 5 V supply tolerance, and provide adequate decoupling. Designers migrating to a modern equivalent should evaluate Altera/Intel MAX II or Lattice ispMACH 4000 CPLDs as the architectural successor; for true drop-in continuity, the EP910PC-35 (same die, plastic DIP) and EP910LI-35 (windowed ceramic DIP) remain in the family.
This page synthesizes Rochester/LCSC distributor pricing, same-family EP910 drop-in alternatives, and practical legacy-design notes not collated in the original Altera datasheet.
کے لیے ڈراپ اِن متبادل EP910PI-35 — یکساں پیکیج، پن سے پن مطابقت پذیر۔ مختلف پیکیج والے پرزے جن کے لیے PCB دوبارہ کام درکار ہو، شامل نہیں ہیں۔
اس سیریز میں مختلف ورژن
اسی سیریز کے ماڈلز جو ڈراپ اِن مطابقت رکھتے ہیں EP910PI-35 (یکساں فارم فیکٹر اور فٹ پرنٹ) — میں مختلف Package, Programming Method, Operating Temperature, Usable Gates, Process Technology.
EP910PC-35
✅ ڈراپ-اِنقیمت کے لیے رابطہ کریں
ڈیٹا شیٹ دیکھیں →EP910LI-35
✅ ڈراپ-اِنقیمت کے لیے رابطہ کریں
ڈیٹا شیٹ دیکھیں →EP910DC-35
✅ ڈراپ-اِنقیمت کے لیے رابطہ کریں
ڈیٹا شیٹ دیکھیں →EP910PI-25
✅ ڈراپ-اِنقیمت کے لیے رابطہ کریں
ڈیٹا شیٹ دیکھیں →EP910PI-30T
✅ ڈراپ-اِنقیمت کے لیے رابطہ کریں
ڈیٹا شیٹ دیکھیں →EP910PI-35 زیادہ سے زیادہ ریٹنگز اور برقی خصوصیات
| Device Family | Altera Classic EPLD (EP910) |
| Logic Elements | 24 Macrocells |
| Usable Gates | 450 |
| Propagation Delay (tPD) | 35 ns |
| Maximum Frequency (fMAX) | 28.6 MHz |
| Supply Voltage (VCC) | 5 V (single supply) |
| Technology | CMOS, UV-erasable EPROM |
| I/O Pins | 24 bidirectional |
| Dedicated Inputs | 12 |
| پیکیج | PDIP-40 (Plastic DIP, through-hole) |
| Programming Method | Legacy Altera programming interface (pre-JTAG) |
| Erasure Method | UV light (windowed variants) / One-time-programmable (this PI suffix) |
| RoHS اسٹیٹس | unknown |
EP910PI-35 پن کنفیگریشن
| پن 1 | I/O0 — Bidirectional I/O pin, macrocell 0 |
| پن 2 | I/O1 — Bidirectional I/O pin, macrocell 1 |
| پن 3 | I/O2 — Bidirectional I/O pin, macrocell 2 |
| پن 4 | I/O3 — Bidirectional I/O pin, macrocell 3 |
| پن 5 | I/O4 — Bidirectional I/O pin, macrocell 4 |
| پن 6 | I/O5 — Bidirectional I/O pin, macrocell 5 |
| پن 7 | I/O6 — Bidirectional I/O pin, macrocell 6 |
| پن 8 | I/O7 — Bidirectional I/O pin, macrocell 7 |
| پن 9 | I/O8 — Bidirectional I/O pin, macrocell 8 |
| پن 10 | I/O9 — Bidirectional I/O pin, macrocell 9 |
| پن 11 | I/O10 — Bidirectional I/O pin, macrocell 10 |
| پن 12 | I/O11 — Bidirectional I/O pin, macrocell 11 |
| پن 13 | INPUT0 — Dedicated input pin 0 |
| پن 14 | INPUT1 — Dedicated input pin 1 |
| پن 15 | INPUT2 — Dedicated input pin 2 |
| پن 16 | INPUT3 — Dedicated input pin 3 |
| پن 17 | INPUT4 — Dedicated input pin 4 |
| پن 18 | INPUT5 — Dedicated input pin 5 |
| پن 19 | INPUT6 — Dedicated input pin 6 |
| پن 20 | INPUT7 — Dedicated input pin 7 |
| پن 21 | INPUT8 — Dedicated input pin 8 |
| پن 22 | INPUT9 — Dedicated input pin 9 |
| پن 23 | INPUT10 — Dedicated input pin 10 |
| پن 24 | INPUT11 — Dedicated input pin 11 |
| پن 25 | I/O12 — Bidirectional I/O pin, macrocell 12 |
| پن 26 | I/O13 — Bidirectional I/O pin, macrocell 13 |
| پن 27 | I/O14 — Bidirectional I/O pin, macrocell 14 |
| پن 28 | I/O15 — Bidirectional I/O pin, macrocell 15 |
| پن 29 | I/O16 — Bidirectional I/O pin, macrocell 16 |
| پن 30 | I/O17 — Bidirectional I/O pin, macrocell 17 |
| پن 31 | I/O18 — Bidirectional I/O pin, macrocell 18 |
| پن 32 | I/O19 — Bidirectional I/O pin, macrocell 19 |
| پن 33 | I/O20 — Bidirectional I/O pin, macrocell 20 |
| پن 34 | I/O21 — Bidirectional I/O pin, macrocell 21 |
| پن 35 | I/O22 — Bidirectional I/O pin, macrocell 22 |
| پن 36 | I/O23 — Bidirectional I/O pin, macrocell 23 |
| پن 37 | GND — Ground |
| پن 38 | VCC — +5 V supply |
| پن 39 | NC — Not connected (per datasheet) |
| پن 40 | NC — Not connected (per datasheet) |
عام استعمالات
EP910PI-35 کے لیے موزوں ہے 6 ایپلیکیشنs: Legacy 80C186/68k Address Decoding Glue Logic, Custom VME/cPCI Peripheral Decoder Logic, TTL MSI State-Machine Replacement, Military/Avionics Display and Control Logic, Industrial PLC I/O Expansion Logic, Test Equipment and ATE Pin-Driver Logic.
Legacy 80C186/68k Address Decoding Glue Logic
The EP910PI-35 fits legacy 16-bit microprocessor systems because its 24 bidirectional I/O pins and 12 dedicated inputs can absorb the address-latch, chip-select, and wait-state logic that would otherwise require 4-6 discrete 74LS/74FCT ICs. The 35 ns tPD comfortably decodes 8 MHz 80C186 bus cycles (which allow ~125 ns per cycle), leaving margin for address-valid to chip-select timing across the full industrial temperature range. Designers typically program the device once with MAX+PLUS II and it runs without reconfiguration for the equipment's entire service life, making it ideal for factory-floor PLCs and instrumentation with 15-20 year field-deployment requirements. The 5 V CMOS I/O also directly interfaces to TTL/CMOS peripherals without level shifters.
تجویز کردہ
Custom VME/cPCI Peripheral Decoder Logic
The EP910PI-35 fits VMEbus and cPCI backplane decoder applications because its 24 macrocells can implement multiple address-window decoders, interrupt acknowledge handlers, and bus-request arbiters in a single chip. The 35 ns propagation delay fits the VMEbus 16 MHz DTB cycle timing with margin for address-valid to DTACK* decoding across industrial temperature extremes. The plastic DIP-40 package also suits the ruggedized through-hole construction preferred in many legacy military and industrial backplane assemblies. With its authorized-continuation status from Rochester Electronics, the EP910PI-35 supports long-lifecycle programs where the VME/cPCI chassis is expected to remain in service for 20+ years.
تجویز کردہ
TTL MSI State-Machine Replacement
The EP910PI-35 fits TTL MSI state-machine replacement because it can replace 4-8 packages of 74LS/74S flip-flops, decoders, and PALs with a single programmable device, reducing PCB area and BOM count in legacy industrial controllers. Each macrocell embeds a flip-flop plus combinatorial logic, so a 24-macrocell EPLD can implement state machines of up to 24 states - covering the vast majority of factory automation sequencer designs. The 35 ns tPD supports state-machine clock rates up to 28.6 MHz, which is well above the typical 1-5 MHz scan rates used in PLC ladder-equivalent logic. Because the design is captured in software (MAX+PLUS II), firmware revisions can be made by re-EPROMing without board rework.
تجویز کردہ
Military/Avionics Display and Control Logic
The EP910PI-35 fits avionics display and control applications because its DIP-40 package, 5 V supply, and Altera EP910 die have decades of flight-qualified heritage and are explicitly listed on Rochester Electronics' authorized-continuation inventory for EOL-prone legacy programs. The 24 macrocells implement discrete-to-discrete logic for cockpit display drivers, mode selectors, and warning-system controllers without the obsolescence risk of newer CPLD families. The 35 ns tPD fits the slow update rates of legacy NTSC-compatible avionics displays (typically 50-60 Hz field refresh with multi-millisecond compute budgets). Rochester's MIL-spec screening and traceable lot records also satisfy DO-254 design-assurance requirements for many legacy platforms.
تجویز کردہ
Industrial PLC I/O Expansion Logic
The EP910PI-35 fits PLC I/O expansion modules because its 24 I/O pins can map directly to a 24-channel digital input or output card, providing per-channel debounce, isolation-buffer logic, and protocol framing in a single chip. The 35 ns tPD handles 100 kHz digital-input sampling rates with margin for contact-bounce filtering and opto-isolator propagation delays. Its CMOS 5 V I/O interfaces to standard 24 V PLC backplanes through external resistor dividers or optocouplers without additional buffer ICs. With Rochester Electronics' authorized-continuation inventory, factory-automation OEMs can keep producing PLC modules whose original Altera EP910 design is no longer risk-free to source from brokers.
تجویز کردہ
Test Equipment and ATE Pin-Driver Logic
The EP910PI-35 fits automatic test equipment (ATE) pin-driver and pattern-generation logic because its 24 macrocells can implement per-pin waveform synthesizers, comparator window-comparators, and fail-capture latches in a single device, replacing racks of discrete ECL/TTL ICs. The 35 ns tPD supports test rates up to ~28 MHz, sufficient for legacy bench-top IC testers targeting TTL/CMOS devices in the 1-25 MHz range. The plastic DIP-40 package is well-suited to ATE fixture cards, which are typically rebuilt every 5-10 years as test programs evolve. Designers can re-program the EPLD in-circuit via the Altera programming header to support new device-under-test (DUT) families without redesigning the fixture.
تجویز کردہ
تجویز کردہ پروڈکٹس کا خلاصہ
کے لیے انجینئرنگ ریفرنس ڈیٹا EP910PI-35 — موازنہ، ڈیزائن رہنمائی، اور تعمیل کی معلومات۔
انتخاب کی گائیڈ
متبادلات کے ساتھ موازنہ
| پیرامیٹر | یہ پروڈکٹ | EP910PC-35 | EP910LI-35 | EP910DC-35 | EP910PI-25 | EP910PI-30 |
|---|---|---|---|---|---|---|
| Brand | Rochester Electronics (Altera die) | Rochester Electronics (Altera die) | Rochester Electronics (Altera die) | Rochester Electronics (Altera die) | Rochester Electronics (Altera die) | Rochester Electronics (Altera die) |
| Package | PDIP-40 | PDIP-40 - same | PDIP-40 - same | PDIP-40 (CERDIP) - same footprint | PDIP-40 - same | PDIP-40 - same |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Usable Gates | 450 | 450 | 450 | 450 | 450 | 450 |
| Propagation Delay (tPD) | 35 ns | 35 ns | 35 ns | 35 ns | 25 ns (-29%, faster) | 30 ns (-14%, faster) |
| Maximum Frequency (fMAX) | 28.6 MHz | 28.6 MHz | 28.6 MHz | 28.6 MHz | ~35.7 MHz (+25%) | ~33.3 MHz (+16%) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Erasure Method | One-time-programmable (OTP) | OTP | UV-erasable (windowed) | UV-erasable (windowed CERDIP) | OTP | OTP |
اہم امتیازی خصوصیات
- Authorized continuation supply from Rochester Electronics (بمقابلہBroker / unauthorized reseller EP910PI-35 stock)
- Plastic DIP-40 form factor (vs windowed ceramic alternatives) (بمقابلہEP910LI-35 (windowed ceramic DIP))
- Mid-range 35 ns speed grade balances cost and timing margin (بمقابلہEP910PI-25 (25 ns speed grade))
ڈیزائن نوٹس
The EP910PI-35 pre-dates JTAG and uses Altera's legacy programming interface. Modern USB-Blaster or JTAG-only programmers will NOT work without an adapter. For prototype programming, use the Altera PL-MPU Master Programming Unit with a DIP-40 adapter socket, or a compatible third-party programmer such as the BP-1200. Design files (JEDEC fuse-map) must be generated with MAX+PLUS II version 10.23 baseline or earlier - newer Quartus software does not support the EP910 family.
Estimated: at 5 V VCC and CMOS input levels, the EP910PI-35 typically draws ~50-100 mA ICC during DC operation and ~150 mA peak during programming pulses. Place a 0.1 uF ceramic decoupling capacitor within 5 mm of the VCC pin (pin 38) and a bulk 10 uF tantalum or aluminum electrolytic on the supply rail. Because the device has only one VCC pin (no separate VCCIO/VCCA), a single 5 V rail suffices, but for designs with high-noise switching converters nearby add an LC pi-filter (10 uH + 10 uF) ahead of the VCC pin.
The DIP-40 footprint uses 2.54 mm (0.100 inch) pin pitch with 0.6 mm (0.024 inch) through-hole pads. Reserve at least 0.5 inch of clearance above the package top for IC extraction tools, and ensure the IC socket (if used) is a high-quality machined-pin type with low contact resistance - press-fit sockets are recommended for any field-replaceable application. For avionics and high-vibration environments, conformal coating is advised and the CERDIP EP910DC-35 variant is preferred for its hermeticity.
The EP910PI-35 35 ns tPD is sufficient for 8-10 MHz bus-cycle decoding but introduces ~3-4 logic-level delays compared to discrete 74FCT gates. When interfacing to fast microprocessors (>16 MHz), use the faster EP910PI-25 or EP910PI-20 speed grade to avoid missing address-valid-to-chip-select timing windows. Unused I/O pins should be configured as outputs driving LOW (or left NC for the JTAG-disabled variants) to minimize power and noise; floating inputs can inject oscillator noise into the internal macrocell array.
تعمیل کی معلومات
Original Altera EP910 family pre-dates RoHS (2006). Rochester Electronics may offer both RoHS-compliant and SnPb lead-bearing variants depending on lot. AEC-Q100 not applicable (industrial/military, not automotive qualified).
