RTAX2000SL-CGS624V vs RTAX2000S-1CGS624EV So sánh
So sánh chi tiết song song của RTAX2000SL-CGS624V bằng Microchip Technology và RTAX2000S-1CGS624EV bằng Microchip Technology. So sánh các thông số quan trọng, thông số điện tử, gói gọn, trạng thái vòng đời, giá cả và khả năng cung cấp để xác định linh kiện tốt nhất cho yêu cầu thiết kế của bạn.
Microchip Technology
RTAX2000SL-CGS624V - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000SL-CGS624V ✓ Hoạt độngMicrochip Technology
RTAX2000S-1CGS624EV - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000S-1CGS624EV ✓ Hoạt độngSo sánh thông số kỹ thuật
| Tham số | RTAX2000SL-CGS624V | RTAX2000S-1CGS624EV |
|---|---|---|
| Thương hiệu | Microchip Technology | Microchip Technology |
| Danh mục | FPGA & CPLD | FPGA & CPLD |
| Trạng thái vòng đời | Hoạt động | Hoạt động |
| Equivalent System Gates | 2000000 | — |
| Logic Cells (CLBs) | 21504 | 21504 |
| Technology | CMOS antifuse (nonvolatile) | — |
| User I/Os (maximum) | 684 | — |
| Embedded Memory | 540 kbits with optional EDAC protection | Embedded SRAM with built-in FIFO control logic |
| Total Ionizing Dose (TID) | 300 krad (Si) functional / 200 krad (Si) parametric | — |
| Single-Event Upset Rate | Less than 1E-10 errors per bit-day | — |
| Configuration | One-time programmable antifuse, live at power-up | One-time programmable anti-fuse, live at power-up, single chip |
| Embedded SRAM Features | Built-in FIFO control logic | — |
| Clock Architecture | Segmentable clock structures | — |
| Routing | Chip-wide highway routing, carry logic | — |
| Hộp | CG624 ceramic package | 624-pin Ceramic Column Grid Array (CGA-624 / CCGA624) |
| Family | RTAX-S/SL Radiation-Tolerant FPGA | — |
| Application Domain | Space-flight systems | — |
| Core Supply Voltage | [DATA_NEEDED: core supply voltage] | 1.5 V nominal (1.425 V to 1.575 V) |
| I/O Supply Voltage | [DATA_NEEDED: I/O supply voltage] | [DATA_NEEDED: I/O bank voltage] |
| Speed Grade | [DATA_NEEDED: speed grade] | — |
| Nhiệt độ hoạt động | [DATA_NEEDED: operating temperature range] | -55C to +125C |
| System Frequency (typical) | [DATA_NEEDED: system frequency] | — |
| System Gates | — | 2,000,000 |
| Total Cells | — | 32256 |
| Additional ASIC Equivalent Gates | — | 250000 |
| Process Technology | — | 0.15 um CMOS |
| Maximum Frequency | — | 649 MHz |
| Logic Family | — | CMOS |
| SEU Immunity | — | SEU-hardened registers, immune to single-event upsets to specified LET threshold |
| SEU Rate | — | < 10-10 errors/bit-day |
| Kiểu lắp đặt | — | Surface Mount |
| Product Family | — | RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs |
| Thermal Resistance Basis | — | JEDEC JESD51 simulation conditions (per datasheet) |
| Maximum User I/O | — | [DATA_NEEDED: user I/O count] |
| Trạng thái RoHS | — | [DATA_NEEDED: RoHS status] |