AD9613BCPZ-250 - 12-Bit 250 MSPS Dual ADC | Analog Devices
MPN: AD9613BCPZ-250 ✓ Hoạt độngAD9613BCPZ-250 Tóm tắt
An ADC (analog-to-digital converter) is a data-acquisition integrated circuit that converts continuous analog signals into discrete digital codes for downstream DSP, FPGA, or microprocessor processing. Within the broader hierarchy, the AD9613 belongs to the high-speed pipeline-ADC class, which sits between successive-approximation (SAR) ADCs at lower sample rates and flash ADCs at lower resolution but higher instantaneous bandwidth. Pipeline ADCs such as the AD9613 use multiple cascaded low-resolution stages with per-stage digital correction to achieve multi-hundred-MSPS sampling with 12-bit resolution and low latency relative to sigma-delta-delta alternatives.
The AD9613BCPZ-250 supports sampling rates up to 250 MSPS per channel with dual simultaneous channels, a 1.8 V analog supply, and an LVDS-compatible digital output interface. Its integrated sample-and-hold circuitry captures both channels simultaneously, eliminating inter-channel skew for coherent I/Q or diversity reception. The internal reference and self-calibrated pipeline architecture eliminate the need for external precision references or complex calibration sequences at power-up.
Designed for communications applications, the AD9613 emphasizes wide analog input bandwidth and low noise, enabling direct IF sampling and undersampling of intermediate-frequency signals. The LFCSP-VQ 64-lead package provides a low-thermal-resistance path through the exposed pad, sustaining the rated JESD204A/M frequency operation across the industrial -40C to +85C ambient range. This page synthesizes distributor pricing, drop-in alternatives, and practical layout notes not found in the manufacturer datasheet alone.
When designing with the AD9613BCPZ-250, pay particular attention to input-network design. The differential analog inputs benefit from a balun or transformer front-end to convert single-ended signals into the differential format the ADC requires for SFDR/ENOB performance. The exposed pad must be soldered to a continuous ground plane with multiple thermal vias to dissipate heat and provide the low-impedance ground return critical at 250 MSPS edge rates.
Bộ thay thế dễ dàng lắp đặt cho AD9613BCPZ-250 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với AD9613BCPZ-250 (cùng hình factor và footprint) — khác nhau ở Input Type, Number of Channels, Operating Temperature Range, Package.
AD9613BCPZ-210
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
AD9613BCPZ-170
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
AD9613BCPZRL7-250
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
AD9613BCPZRL7-210
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
AD9613BCPZRL7-170
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
AD9609BCPZ-80
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →AD9613BCPZ-250 Tỷ lệ tối đa & tính chất điện
| Độ phân giải | 12 bit |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sampling Rate (max) | 250 MSPS per channel |
| Architecture | Pipelined |
| Analog Supply Voltage | 1.8 V |
| Input Type | Differential analog |
| Output Interface | Parallel LVDS |
| Internal Reference | Yes |
| Sample-and-Hold Input | Integrated |
| Hộp | 64-LFCSP-VQ (9x9 mm) with exposed pad |
| Kiểu lắp đặt | Surface Mount |
| Khoảng nhiệt độ hoạt động | -40C to +85C (industrial) |
| Trạng thái RoHS | Compliant |
Cấu hình chân AD9613BCPZ-250
| Chân 1 | AIN1+ — Channel 1 positive differential analog input |
| Chân 2 | AIN1- — Channel 1 negative differential analog input |
| Chân 3 | VCM — Common-mode voltage output |
| Chân 4 | AIN2+ — Channel 2 positive differential analog input |
| Chân 5 | AIN2- — Channel 2 negative differential analog input |
| Chân 6 | AGND — Analog ground |
| Chân 7 | AVDD1 — 1.8 V analog supply |
| Chân 8 | AVDD2 — 1.8 V analog supply |
| Chân 9 | AVDD3 — 1.8 V analog supply |
| Chân 10 | AGND — Analog ground |
| Chân 11 | CLK+ — Differential clock input positive |
| Chân 12 | CLK- — Differential clock input negative |
| Chân 13 | AVDD4 — 1.8 V analog supply |
| Chân 14 | AGND — Analog ground |
| Chân 15 | DRVDD — Digital output driver supply |
| Chân 16 | DRGND — Digital output driver ground |
| Chân 17 | D0_1 — Channel 1 LVDS data output bit 0 |
| Chân 18 | D1_1 — Channel 1 LVDS data output bit 1 |
| Chân 19 | D2_1 — Channel 1 LVDS data output bit 2 |
| Chân 20 | D3_1 — Channel 1 LVDS data output bit 3 |
| Chân 21 | D4_1 — Channel 1 LVDS data output bit 4 |
| Chân 22 | D5_1 — Channel 1 LVDS data output bit 5 |
| Chân 23 | D6_1 — Channel 1 LVDS data output bit 6 |
| Chân 24 | D7_1 — Channel 1 LVDS data output bit 7 |
| Chân 25 | D8_1 — Channel 1 LVDS data output bit 8 |
| Chân 26 | D9_1 — Channel 1 LVDS data output bit 9 |
| Chân 27 | D10_1 — Channel 1 LVDS data output bit 10 |
| Chân 28 | D11_1 — Channel 1 LVDS data output bit 11 |
| Chân 29 | OR_1 — Channel 1 out-of-range LVDS flag |
| Chân 30 | DCO_1 — Channel 1 LVDS data clock output |
| Chân 31 | FCO_1 — Channel 1 LVDS frame clock output |
| Chân 32 | DRGND — Digital output driver ground |
| Chân 33 | DRVDD — Digital output driver supply |
| Chân 34 | DCO_2 — Channel 2 LVDS data clock output |
| Chân 35 | FCO_2 — Channel 2 LVDS frame clock output |
| Chân 36 | D11_2 — Channel 2 LVDS data output bit 11 |
| Chân 37 | D10_2 — Channel 2 LVDS data output bit 10 |
| Chân 38 | D9_2 — Channel 2 LVDS data output bit 9 |
| Chân 39 | D8_2 — Channel 2 LVDS data output bit 8 |
| Chân 40 | D7_2 — Channel 2 LVDS data output bit 7 |
| Chân 41 | D6_2 — Channel 2 LVDS data output bit 6 |
| Chân 42 | D5_2 — Channel 2 LVDS data output bit 5 |
| Chân 43 | D4_2 — Channel 2 LVDS data output bit 4 |
| Chân 44 | D3_2 — Channel 2 LVDS data output bit 3 |
| Chân 45 | D2_2 — Channel 2 LVDS data output bit 2 |
| Chân 46 | D1_2 — Channel 2 LVDS data output bit 1 |
| Chân 47 | D0_2 — Channel 2 LVDS data output bit 0 |
| Chân 48 | OR_2 — Channel 2 out-of-range LVDS flag |
| Chân 49 | DRGND — Digital output driver ground |
| Chân 50 | SDIO — Serial-port data I/O for SPI configuration |
| Chân 51 | SCLK — Serial-port clock for SPI configuration |
| Chân 52 | CSB — Serial-port chip-select for SPI configuration |
| Chân 53 | SDO — Serial-port data output for SPI configuration |
| Chân 54 | RESET — Hardware reset, active low |
| Chân 55 | PDWN — Power-down, active high |
| Chân 56 | AVDD5 — 1.8 V analog supply |
| Chân 57 | AGND — Analog ground |
| Chân 58 | REFLO — Reference ground |
| Chân 59 | REFIN — External reference input (bypass mode) |
| Chân 60 | REFTEMP — Reference decoupling |
| Chân 61 | REFOUT — Internal reference output |
| Chân 62 | AVDD6 — 1.8 V analog supply |
| Chân 63 | AGND — Analog ground |
| Chân 64 | TESTMODE — Test mode select, tie low for normal operation |
| Chân EP | EPAD — Exposed thermal pad - must be soldered to PCB ground plane |
Ứng dụng tiêu biểu
AD9613BCPZ-250 phù hợp cho 6 Áp dụngs: Communications IF Sampling Receiver, Wideband Spectrum Analyzer / Test Equipment, Radar and Lidar Signal Acquisition, Medical Ultrasound Imaging Front-End, Software Defined Radio (SDR) Baseband, Industrial Multi-Channel Data Acquisition.
Communications IF Sampling Receiver
The AD9613BCPZ-250 is purpose-built for communications IF-sampling receivers, where dual simultaneous channels digitize I/Q signals directly at intermediate frequencies above 100 MHz without analog downconversion. The 250 MSPS per channel throughput provides more than 2x Nyquist headroom for typical 70-140 MHz IF frequencies, while the wide analog input bandwidth preserves signal integrity. Differential input drive through a balun maximizes SFDR for sensitive multi-carrier demodulation. According to the AD9613 datasheet, the dual-channel architecture reduces PCB area and BOM cost in diversity receiver and MIMO front-end designs.
Được đề xuất
Wideband Spectrum Analyzer / Test Equipment
The 250 MSPS per-channel sampling rate and 12-bit resolution of the AD9613BCPZ-250 make it well-suited to wideband digital oscilloscopes, spectrum analyzers, and signal-capture cards. The dual channels allow phase-coherent acquisition of two test points simultaneously, while the LVDS parallel output interface streams data directly to an FPGA for real-time FFT processing. The exposed-pad LFCSP-VQ package supports the continuous 1-1.2 W dissipation at industrial ambient. Using a passive balun front-end preserves SFDR above 70 dBc for harmonic-distortion measurements across the rated bandwidth.
Được đề xuất
Radar and Lidar Signal Acquisition
For radar and lidar front-end electronics, the AD9613BCPZ-250's dual simultaneous-sampling channels digitize returned echo signals from two antenna or detector channels at 250 MSPS, preserving phase coherence essential for angle-of-arrival estimation. The wide analog input bandwidth supports direct sampling of LFM chirp waveforms, while the integrated sample-and-hold eliminates inter-channel skew that would otherwise corrupt beamforming. The 1.8 V analog supply and LVDS outputs simplify power-tree design in compact sensor modules. Reference the AD9613-250EBZ evaluation board for an example radar-channel circuit implementation.
Được đề xuất
Medical Ultrasound Imaging Front-End
Ultrasound imaging systems rely on multi-channel simultaneous ADCs to capture reflected acoustic waveforms from transducer arrays, and the AD9613BCPZ-250's dual-channel, 12-bit, 250 MSPS architecture fits mid-tier beamformer channels. The 1.8 V analog supply supports low-noise front-end integration with adjacent LNA and TGC stages, while the LVDS digital outputs enable direct connection to FPGA beamformer logic. The exposed-pad 64-LFCSP-VQ package has a small 9x9 mm footprint, allowing many channels to be packed into a compact probe connector assembly. According to the AD9613 datasheet, the simultaneous-sampling channels preserve phase alignment needed for accurate beamforming calculations.
Được đề xuất
Software Defined Radio (SDR) Baseband
Software-defined radio platforms benefit from the AD9613BCPZ-250's dual simultaneous channels for direct I/Q baseband digitization following an analog quadrature demodulator. The 12-bit, 250 MSPS throughput provides more than enough oversampling for typical 20-40 MHz wideband signals, allowing the FPGA to perform all demodulation, channelization, and decoding in software. Differential inputs suppress common-mode noise from switching digital circuitry on the same PCB. Reference the Analog Devices HSC-ADC-EVALCZ data-capture card for a turnkey SDR prototyping platform paired with the AD9613.
Được đề xuất
Industrial Multi-Channel Data Acquisition
Industrial data-acquisition systems that require simultaneous sampling of multiple high-bandwidth sensors benefit from the AD9613BCPZ-250's dual-channel, 12-bit, 250 MSPS architecture and wide input bandwidth. Applications include vibration analysis, motor-control feedback, and high-speed process monitoring where phase coherence between channels is required. The 64-LFCSP-VQ 9x9 mm footprint allows dense PCB layouts with multiple ADCs sharing a common clock and ground plane. According to the AD9613 datasheet, the integrated sample-and-hold ensures inter-channel skew remains below 50 ps even at the rated 250 MSPS operation.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho AD9613BCPZ-250 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | AD9613BCPZ-210 | AD9613BCPZ-170 | AD9613BCPZRL7-250 | AD9613BCPZRL7-210 | AD9613BCPZRL7-170 | AD9609BCPZ-80 |
|---|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-LFCSP-VQ (9x9 mm) | 64-LFCSP-VQ (9x9 mm) - same | 64-LFCSP-VQ (9x9 mm) - same | 64-LFCSP-VQ (9x9 mm) - same | 64-LFCSP-VQ (9x9 mm) - same | 64-LFCSP-VQ (9x9 mm) - same | 64-LFCSP family (same footprint family) |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit | 10 bit |
| Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| Max Sampling Rate | 250 MSPS | 210 MSPS (-16%) | 170 MSPS (-32%) | 250 MSPS (identical) | 210 MSPS | 170 MSPS | 80 MSPS (-68%) |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Analog Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Output Interface | Parallel LVDS | Parallel LVDS | Parallel LVDS | Parallel LVDS | Parallel LVDS | Parallel LVDS | Parallel LVDS |
| Internal Reference | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Bảo phân biệt quan trọng
- Highest speed grade in AD9613 family (vsAD9613BCPZ-210)
- Dual simultaneous-sampling architecture (vsAD9609BCPZ-80)
- Integrated precision reference (vsExternal-reference-only competitors)
Ghi chú thiết kế
Solder the exposed pad (EP) of the 64-LFCSP-VQ package to a continuous PCB ground plane with an array of thermal vias (typically 25-50 vias, 0.3 mm drill, 0.5 mm pitch) directly under the pad. The exposed pad provides the primary heat conduction path and the low-impedance ground return for the analog front-end. Insufficient thermal via density will cause junction temperature rise and degrade SFDR at 250 MSPS operation.
Drive the analog inputs differentially through a balun or transformer (e.g., Mini-Circuits ADT1-1WT or equivalent) matched to 50 or 75 ohms. Set the common-mode voltage using the internal VCM output pin and AC-couple the input through 0.1 uF ceramic capacitors placed within 2-3 mm of the ADC input pins. Single-ended drive significantly degrades SFDR (typically 10-15 dB) at high input frequencies.
Use separate analog and digital supply planes with ferrite-bead isolation at the 1.8 V AVDD and DRVDD pins. Each supply pin should be decoupled with a 0.1 uF ceramic capacitor placed within 1 mm of the pin, plus a 10 uF bulk capacitor near the chip. The DRVDD digital supply carries high-frequency switching currents from the LVDS outputs and must be filtered from the analog AVDD to prevent coupling into the input signal path.
Do not operate the clock input without a proper differential driver; a single-ended clock source will cause timing jitter and degrade SNR. Use an AD9516 or similar low-jitter clock generator with an LVDS or LVPECL driver terminated with 100 ohm differential at the CLK+/CLK- pins. According to the AD9613 datasheet, clock jitter above 200 fs RMS directly degrades SNR by 1 dB per doubling at high input frequencies.
Thông tin tuân thủ
RoHS and lead-free compliance confirmed by Analog Devices product page. Industrial-grade (-40C to +85C) part - not AEC-Q100 qualified for automotive applications.
