EP910PC-15T - 24-Macrocell EPLD, 15ns, PDIP-40 | Altera Classic
MPN: EP910PC-15T ✗ Cuối đờiEP910PC-15T Tóm tắt
An EPLD (Erasable Programmable Logic Device) is a member of the programmable logic hierarchy, sitting between simple PLDs (PAL/GAL) and modern FPGAs/CPLDs. EPLDs use a sum-of-products architecture with a programmable AND array feeding fixed OR gates and output macrocells, packaged in UV-erasable or one-time-programmable CMOS silicon. The Classic family was Altera's second-generation EPLD line, replacing discrete TTL/CMOS gate arrays with single-chip, user-programmable logic for glue functions, state machines, and bus-interface logic.
Key features include 24 macrocells each containing a programmable flip-flop with separate feedback, output enable, and programmable output polarity, plus 10 dedicated input pins (no input/output pin multiplexing) that simplify pin-locked designs. Device programming uses the Altera LogicMap or MAX+PLUS II design flow with industry-standard JEDEC fuse-map files. The EP910 also supports security-bit protection to lock the design after programming.
Architecturally, the EP910 implements a global bus-driven AND plane with 72 product terms feeding 24 macrocells, yielding 24 registered outputs that can be configured as combinational (bypass register) or registered. The device is non-volatile (UV-erasable on ceramic-windowed versions, OTP on plastic packages), operates from a single 5 V supply, and delivers TTL-compatible I/O with 24 mA sink current per output.
Typical applications include bus-interface glue logic, address decoding for microprocessor systems, peripheral control state machines, and replacement of multiple discrete 74LS/74F TTL parts. Modern designs typically substitute the EP910 with a CoolRunner-II CPLD or MAX II CPLD, but the Classic EP910 remains in service for legacy industrial, military, and avionics systems where pin-compatible replacements are required.
Design considerations: the 15 ns speed grade is the slowest in the EP910 family (the family spans 10-25 ns); the suffix '-15T' includes tape-and-reel packaging. Plan for end-of-life risk - Altera discontinued the Classic EPLD family years ago, so sourcing is limited to authorized distributors and the broker/excess market.
This page synthesizes datasheet parameters, drop-in Altera Classic family variants, parametric comparison data, and practical design notes not found in a single manufacturer document.
Bộ thay thế dễ dàng lắp đặt cho EP910PC-15T — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EP910PC-15T (cùng hình factor và footprint) — khác nhau ở Package, Supply Voltage (VCC), Technology, Family, Dedicated Inputs.
EP910PC-15
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910PC-25
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910PC-30
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910LC-40
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910DC-15
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910PC-15T Tỷ lệ tối đa & tính chất điện
| Product Type | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD |
| Macrocell Count | 24 |
| Dedicated Input Pins | 10 |
| Pin-to-Pin Delay (tPD) | 15 ns |
| Speed Grade | -15 (15 ns) |
| Supply Voltage (VCC) | 5 V (nominal) |
| Technology | CMOS, UV-erasable / OTP |
| Hộp | 40-pin PDIP (Plastic DIP) |
| Kiểu lắp đặt | Through-hole (DIP) |
| Nhiệt độ hoạt động | 0C to +70C (commercial) |
| Logic Capacity | 24 macrocells / 72 product terms (typical Classic architecture) |
| Programming Method | JEDEC fuse map via Altera LogicMap / MAX+PLUS II |
| Security Bit | Yes (design protection) |
| Tape and Reel | Yes (suffix T) |
Cấu hình chân EP910PC-15T
| Chân 1 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 2 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 3 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 4 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 5 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 6 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 7 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 8 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 9 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 10 | GND — Ground |
| Chân 11 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 12 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 13 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 14 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 15 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 16 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 17 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 18 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 19 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 20 | GND — Ground |
| Chân 21 | INPUT — Dedicated input pin |
| Chân 22 | INPUT — Dedicated input pin |
| Chân 23 | INPUT — Dedicated input pin |
| Chân 24 | INPUT — Dedicated input pin |
| Chân 25 | INPUT — Dedicated input pin |
| Chân 26 | VCC — +5 V supply |
| Chân 27 | INPUT — Dedicated input pin |
| Chân 28 | INPUT — Dedicated input pin |
| Chân 29 | INPUT — Dedicated input pin |
| Chân 30 | INPUT — Dedicated input pin |
| Chân 31 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 32 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 33 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 34 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 35 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 36 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 37 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 38 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 39 | I/O — Macrocell I/O - bidirectional logic pin |
| Chân 40 | VCC — +5 V supply |
Ứng dụng tiêu biểu
EP910PC-15T phù hợp cho 6 Áp dụngs: Microprocessor Bus Address Decoding, Legacy Industrial Control Logic Replacement, Peripheral Control State Machines, Avionics and Military Legacy Sustainment, Bus Interface and Glue Logic Bridging, Telecom Backplane Signal Conditioning.
Microprocessor Bus Address Decoding
The EP910PC-15T is well suited for microprocessor bus address-decoding applications because its 24 macrocells can implement multi-level chip-select logic for memory and peripheral banks. With 15 ns tPD, the device delivers decoded chip-selects within one 8 MHz 8051 bus cycle or a 25 MHz 8086 T-state. According to the Altera EP910 datasheet, the 10 dedicated inputs accept address and control signals without I/O pin contention, simplifying pin-locked bus-interface designs. The bipolar-TTL-compatible outputs drive 24 mA per pin, sufficient to directly sink peripheral enable lines.
Được đề xuất
Legacy Industrial Control Logic Replacement
The EP910PC-15T replaces clusters of discrete 74LS/74F TTL gates in legacy industrial control designs. Each of the 24 macrocells consumes roughly 12 mW at 5 V/5 MHz, so a single EP910 replaces up to 24 SSI/MSI packages and reduces board area by 60-70%. Per the manufacturer datasheet, the Classic EPLD's programmable polarity and output enable make it ideal for replacing wired-OR/AND glue logic in PLC and motor-control backplanes where downtime cost dominates redesign cost.
Được đề xuất
Peripheral Control State Machines
The EP910PC-15T's 24 macrocells each contain a D flip-flop with separate clock and feedback, making it efficient for implementing multi-state peripheral controllers (e.g., SCSI handshaking, GPIB talker/listener, parallel-port state decoders). The dedicated input pins (10) feed the global AND plane with 72 product terms, sufficient for 3-state controllers. According to Altera, Classic EPLDs support both Mealy and Moore state-machine topologies with up to 24 states - ideal for instrument-control firmware that must remain bit-compatible with older designs.
Được đề xuất
Avionics and Military Legacy Sustainment
The EP910PC-15T remains in service for avionics and military legacy systems where the Classic EPLD is qualified by baseline design and qualification testing cannot be re-run. The plastic PDIP-40 package suits commercial avionics; the EP910DC-15 (ceramic DIP) and EP910DM/883B variants satisfy MIL-STD-883 processing. Per the manufacturer datasheet, the Classic family is rated for -55C to +125C operation in military-grade packaging, and Rochester Electronics holds ongoing factory-traceable stock for legacy sustainment contracts.
Được đề xuất
Bus Interface and Glue Logic Bridging
The EP910PC-15T is widely deployed as glue logic between mismatched bus standards - for example, converting 5 V TTL control signals to 3.3 V CMOS peripheral interfaces through external resistor networks while performing protocol translation. The 24 programmable I/O pins plus 10 dedicated inputs allow both data-path and control-signal fan-in to coexist. With 15 ns propagation delay, the device keeps inserted wait-states below 1 cycle for 25 MHz buses, making it useful for VME, ISA, and PC/104 backplanes still in service.
Được đề xuất
Telecom Backplane Signal Conditioning
The EP910PC-15T is deployed in telecom backplanes for line-interface signal conditioning, retiming, and alarm-state generation. Its registered macrocells implement retiming flip-flops while the AND plane generates alarm-aggregation logic from multiple line feeds. Per Altera datasheet, the 24 mA sink current directly drives optocoupler LEDs in line-interface cards, eliminating driver buffers. Although newer designs use MAX II CPLDs, EP910PC-15T sustainment continues for installed-base telecom equipment with FCC part 68 type approval.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho EP910PC-15T — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | EP910PC-15 | EP910PC-25 | EP910PC-30 | EP910LC-40 | EP910DC-15 |
|---|---|---|---|---|---|---|
| Package | PDIP-40 | PDIP-40 (tube) | PDIP-40 | PDIP-40 | PDIP-40 | CDIP-40 (ceramic) |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocell Count | 24 | 24 | 24 | 24 | 24 | 24 |
| Pin-to-Pin Delay (tPD) | 15 ns | 15 ns | 25 ns | 30 ns | 40 ns | 15 ns |
| Dedicated Input Pins | 10 | 10 | 10 | 10 | 10 | 10 |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | -55C to +125C (military) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Packaging Format | Tape & Reel | Tube | Tube | Tube | Tube | Tube (ceramic) |
Bảo phân biệt quan trọng
- Fastest speed grade available in PDIP-40 (vsEP910PC-25)
- Tape and Reel packaging for automated assembly (vsEP910PC-15)
- Pin-compatible family breadth (vsEP610PC-25 (16-macrocell family))
Ghi chú thiết kế
Estimated: The EP910PC-15T draws approximately 200 mA at 5 V with all 24 macrocells toggling at 5 MHz, dissipating roughly 1 W. With theta_JA around 50 C/W for the PDIP-40 package, junction temperature rises about 50 C above ambient at full activity - within commercial 0-70C ratings for typical office environments but inadequate for sealed enclosures. For sealed industrial housings, derate activity by 50% or substitute the EP910LC-40 low-power variant.
Classic EPLDs require a dedicated legacy Altera programming fixture (LogicMap or MAX+PLUS II) that is no longer manufactured. Before committing to the EP910PC-15T in a production design, confirm in-house availability of a working programmer and a source of blank parts, or plan for third-party programming services such as Rochester Electronics. New designs should default to MAX II/MAX V CPLDs with USB-based programmers.
Place 0.1 uF decoupling capacitors on every VCC pin pair (PDIP-40 has two VCC pins: pins 26 and 40). For through-hole PDIP construction, use 0.1 uF ceramic caps with leads as short as possible, plus a single 10 uF tantalum bulk cap near each VCC pin. Keep programming-pin traces short if an in-circuit programming header is used; long traces pick up noise that can corrupt the fuse-map download.
Substituting a slower speed grade (e.g., EP910PC-30 for EP910PC-15T) violates timing in designs that depend on the 15 ns tPD - typically bus decoders, chip-select generators, or state-machine feedback. Validate the new timing margin using worst-case PVT simulation or by bench-measuring the failing path before committing to a downgrade. Never substitute a slower grade without explicit timing verification.
Thông tin tuân thủ
RoHS/REACH/lead-free status not confirmed in available web data; Classic EPLDs predate widespread RoHS adoption. AEC-Q100 not applicable (this is a programmable logic device, not an automotive-grade analog/power IC).
