EP910PI-35T - 24-Macrocell Classic EPLD, 35ns, PDIP-40 | Altera
MPN: EP910PI-35T ✗ Cuối đờiEP910PI-35T Tóm tắt
A Classic EPLD is an electrically erasable programmable logic device that preceded modern CPLDs, integrating multiple PAL/GAL-type functions into a single CMOS IC. The Classic family hierarchy sits within Erasable PLD -> PLD -> Programmable Logic -> Digital Logic IC -> Semiconductor, providing glue-logic integration, bus decoding, and state-machine consolidation in systems built before low-cost FPGAs dominated the market.
The EP910 integrates 24 macrocells across 450 usable gates, supports 100% TTL emulation, and includes on-board logic test circuitry for AC specification verification during production. The device is reprogrammable via UV erasure, supports 5V VCC operation, and exposes JTAG-like boundary-scan testability in higher-grade variants. Architecture features a global interconnect matrix, 24 product-term-driven flip-flop macrocells, and pin-to-pin delays as fast as 35ns for the -35 speed grade.
Typical applications include address decoding for 8-bit/16-bit microprocessor systems, glue-logic consolidation in legacy industrial controllers, state-machine implementation in test equipment, and bus-interface bridging between asynchronous peripherals. The wide 5V tolerance and 100% TTL emulation make it well suited to replace discrete 74LS/74F logic on legacy boards without level-shifting.
When designing with this device, ensure the 5V supply is well decoupled with 0.1uF ceramic capacitors placed within 5mm of the VCC and GND pins, and reserve the global clock pin for high-frequency synchronous logic to minimize skew. Inputs exceeding VCC by more than 0.5V should be clamped, since EP910 outputs drive TTL but the input structures are CMOS.
This page synthesizes distributor pricing, pin-compatible Classic EPLD drop-in alternatives, and practical design notes not aggregated on any single manufacturer or distributor product page, providing engineering value beyond the datasheet PDF alone.
Bộ thay thế dễ dàng lắp đặt cho EP910PI-35T — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EP910PI-35T (cùng hình factor và footprint) — khác nhau ở Package, Supply Voltage (VCC), Usable Gates, Technology, Family.
EP910PI-35
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910PC-35
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910LC-35
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910PI-30T
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910PC-30
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910PC-25
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910PI-35T Tỷ lệ tối đa & tính chất điện
| Family | Altera Classic EPLD |
| Device Type | Erasable Programmable Logic Device (EPLD) |
| Macrocells | 24 |
| Usable Gates | 450 |
| Pin-to-Pin Logic Delay (tpd) | 35 ns |
| Counter Frequency (fCNT) | 28.6 MHz |
| Supply Voltage (VCC) | 5 V |
| I/O Logic Compatibility | 100% TTL emulation |
| Process Technology | CMOS |
| Hộp | 40-pin PDIP (Plastic DIP) |
| Kiểu lắp đặt | Through-Hole |
| Programming Method | UV-erasable, EPROM technology |
| On-board Test Circuitry | Yes (logic test mode for AC verification) |
Cấu hình chân EP910PI-35T
| Chân 1 | I/O — Macrocell I/O pin 1 |
| Chân 2 | I/O — Macrocell I/O pin 2 |
| Chân 3 | I/O — Macrocell I/O pin 3 |
| Chân 4 | I/O — Macrocell I/O pin 4 |
| Chân 5 | I/O — Macrocell I/O pin 5 |
| Chân 6 | I/O — Macrocell I/O pin 6 |
| Chân 7 | I/O — Macrocell I/O pin 7 |
| Chân 8 | I/O — Macrocell I/O pin 8 |
| Chân 9 | I/O — Macrocell I/O pin 9 |
| Chân 10 | GND — Ground |
| Chân 11 | I/O — Macrocell I/O pin 11 |
| Chân 12 | I/O — Macrocell I/O pin 12 |
| Chân 13 | I/O — Macrocell I/O pin 13 |
| Chân 14 | I/O — Macrocell I/O pin 14 |
| Chân 15 | I/O — Macrocell I/O pin 15 |
| Chân 16 | I/O — Macrocell I/O pin 16 |
| Chân 17 | I/O — Macrocell I/O pin 17 |
| Chân 18 | I/O — Macrocell I/O pin 18 |
| Chân 19 | I/O — Macrocell I/O pin 19 |
| Chân 20 | GND — Ground |
| Chân 21 | I/O — Macrocell I/O pin 21 |
| Chân 22 | I/O — Macrocell I/O pin 22 |
| Chân 23 | I/O — Macrocell I/O pin 23 |
| Chân 24 | I/O — Macrocell I/O pin 24 |
| Chân 25 | I/O — Macrocell I/O pin 25 |
| Chân 26 | I/O — Macrocell I/O pin 26 |
| Chân 27 | I/O — Macrocell I/O pin 27 |
| Chân 28 | I/O — Macrocell I/O pin 28 |
| Chân 29 | I/O — Macrocell I/O pin 29 |
| Chân 30 | GND — Ground |
| Chân 31 | I/O — Macrocell I/O pin 31 |
| Chân 32 | I/O — Macrocell I/O pin 32 |
| Chân 33 | I/O — Macrocell I/O pin 33 |
| Chân 34 | I/O — Macrocell I/O pin 34 |
| Chân 35 | CLK — Global clock input |
| Chân 36 | OE — Output enable (active low) |
| Chân 37 | I/O — Macrocell I/O pin 37 |
| Chân 38 | I/O — Macrocell I/O pin 38 |
| Chân 39 | VCC — +5V supply |
| Chân 40 | VCC — +5V supply |
Ứng dụng tiêu biểu
EP910PI-35T phù hợp cho 6 Áp dụngs: Address Decoding in Microprocessor Systems, Glue-Logic Consolidation on Legacy Industrial Boards, State-Machine Implementation in Test Equipment, Bus-Interface Bridging Between Peripherals, Retro Computing and Vintage Hardware Restoration, Educational PLD Development Platform.
Address Decoding in Microprocessor Systems
The EP910PI-35T fits address decoding in 8-bit and 16-bit microprocessor systems because its 24 macrocells can implement a complete chip-select decoder for memory and peripheral address spaces. The 35ns pin-to-pin delay adds less than one 8 MHz clock cycle of propagation, leaving ample timing margin for 8086, 68000, and Z80 buses running at full speed. Place the EP910 between the processor address bus and the chip-select pins of memory/peripheral devices, programming it via MAX+PLUS II to generate active-low or active-high CS signals as needed.
Được đề xuất
Glue-Logic Consolidation on Legacy Industrial Boards
The EP910PI-35T is well suited to consolidate discrete 74LS, 74F, and 74HC glue logic on legacy industrial controller boards where redesigns are cost-prohibitive. The 24 macrocells replace typically 4-8 SSI/MSI packages (decoders, muxes, latches), reducing PCB area and improving reliability by removing solder joints. The 5V supply and 100% TTL I/O compatibility allow direct substitution of the EP910 onto existing 5V logic rails without level shifting or pull-up resistor networks.
Được đề xuất
State-Machine Implementation in Test Equipment
The EP910PI-35T implements dedicated control state machines in test and measurement equipment where deterministic 35ns propagation is critical for synchronized instrument timing. Its 24 macrocells support Mealy or Moore state machines with up to 16 states plus output decode logic. The on-board logic test circuitry enables AC verification during production flow, helping test-equipment OEMs confirm timing margins before shipping. Operate the EP910 on a clean 5V rail with the global clock pin reserved for synchronous state transitions to minimize clock-to-output skew.
Được đề xuất
Bus-Interface Bridging Between Peripherals
The EP910PI-35T bridges asynchronous peripheral buses by translating protocol signals and generating handshake timing, fitting applications where two peripherals with incompatible timing must interoperate. The 24 macrocells implement both sides of a bus bridge with sufficient headroom for FIFO pointers, address mapping, and interrupt arbitration logic. At 35ns delay, the bridge is suitable for peripheral buses operating up to approximately 10 MHz, covering ISA, PC/104, and similar legacy interconnects.
Được đề xuất
Retro Computing and Vintage Hardware Restoration
The EP910PI-35T is widely used in retro-computing hobbyist restoration projects for 1980s and 1990s computer systems where original Altera Classic EPLDs have failed. The 40-pin PDIP form factor matches the original through-hole sockets, and the 5V TTL interface is compatible with vintage TTL logic families without modification. Hobbyists source EP910PI-35T or its PC/LC equivalents from Rochester Electronics or FPGAkey distributors to restore XT/AT-class systems, S-100 bus peripherals, and similar legacy hardware.
Được đề xuất
Educational PLD Development Platform
The EP910PI-35T serves as a teaching platform in university digital-logic courses where students learn MAX+PLUS II design entry, simulation, and device programming on a real through-hole PLD. The 24-macrocell capacity is sufficient for student projects covering counters, multiplexers, simple state machines, and small ALUs. The 40-pin PDIP package fits standard breadboards and wire-wrap prototyping boards, allowing students to verify designs on hardware without requiring SMT rework capability.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho EP910PI-35T — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | EP910PI-35 | EP910PC-35 | EP910LC-35 | EP910PI-30T | EP910PC-25 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PDIP-40 | PDIP-40 (same) | PDIP-40 (same) | CDIP-40 (same footprint, ceramic) | PDIP-40 (same) | PDIP-40 (same) |
| Speed Grade (tpd) | 35 ns | 35 ns | 35 ns | 35 ns | 30 ns (faster) | 25 ns (faster) |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Usable Gates | 450 | 450 | 450 | 450 | 450 | 450 |
| Counter Frequency (fCNT) | 28.6 MHz | 28.6 MHz | 28.6 MHz | 28.6 MHz | 33.3 MHz | 40 MHz |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Package Type | Plastic DIP | Plastic DIP | Plastic DIP (commercial) | Ceramic DIP (military/industrial) | Plastic DIP | Plastic DIP |
Bảo phân biệt quan trọng
- Tape-and-reel packaging for automated assembly (vsEP910PI-35)
- Broader legacy stock availability (vsEP910PI-30T)
- Plastic DIP form factor optimized for cost (vsEP910LC-35)
Ghi chú thiết kế
The EP910PI-35T operates from a single 5V supply and requires local decoupling of every VCC/GND pair with a 0.1uF ceramic capacitor placed within 5mm of the package pins. The Classic EPLD has high transient current spikes during simultaneous output switching on multiple macrocells, so a bulk 10uF tantalum or aluminum electrolytic capacitor should be placed near the VCC pins. Ground bounce on shared GND pins can cause spurious logic transitions in fast designs; route ground returns on a continuous ground plane under the DIP footprint to minimize inductance.
Inputs to the EP910 must not exceed VCC by more than 0.5V. Although outputs are TTL-compatible, the input structures are CMOS and can be damaged by voltage excursions above VCC during hot-swap events or power-supply sequencing faults. In designs where 5V signals may be applied before the EP910 VCC rail stabilizes, add clamp diodes or current-limiting resistors on each input. Always use the global clock pin for synchronous logic and avoid using it as a general-purpose I/O - the dedicated clock routing tree has lower skew than the regular interconnect matrix.
The 40-pin PDIP has a 2.54mm (0.1 inch) pin pitch and through-hole mounting. Reserve generous copper pours around VCC and GND pins to carry the transient switching current. For socketed designs, use machined-pin DIP sockets rather than low-cost stamped sockets to ensure reliable contact over thermal cycling. The exposed leads on PDIP packages can be trimmed flush before insertion into low-profile card-edge assemblies; trim length should not exceed 0.5mm to avoid creating inductive stubs on the VCC/GND leads.
Thông tin tuân thủ
RoHS compliance status not confirmed in the verified web data; this part predates widespread RoHS transition and is typically supplied as a legacy Altera product. AEC-Q100 is not applicable since EP910 is not marketed for automotive applications.
