EP910PI-20 - 24 Macrocell Classic EPLD, 20ns, PDIP-40 | Altera
MPN: EP910PI-20 ✗ Cuối đờiEP910PI-20 Tóm tắt
Background Knowledge: An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device, sitting in the broader taxonomy of programmable logic: PLD -> EPLD -> CPLD -> programmable logic -> semiconductor. EPLDs were the predecessors to today's CPLDs and offer a small number of macrocells with deterministic timing and zero power-on configuration delay, unlike SRAM-based FPGAs. They were widely used for address decoding, bus arbitration, state-machine control, and peripheral glue logic in 5V-era designs. The EP910 family is the 24-macrocell, 36-pin/40-pin member of the original Altera Classic series, with EP610 (16 macrocells) and EP1810 (48 macrocells) as siblings.
Key features of the EP910PI-20 include 24 macrocells organized as 12 dedicated inputs and 24 bidirectional I/O pins (in the PDIP-40 footprint), 20 ns tPD (pin-to-pin delay), a 125 MHz internal counter frequency, and zero standby-power CMOS EPROM technology with UV-erasable windowed packages available for prototyping. The device is 5V-tolerant (VCC = 5V +/- 5%) and offers programmable macrocell flip-flops, product-term allocation, and configurable output polarity. The PI suffix indicates the industrial temperature grade (-40C to +85C).
Architecturally, the EP910 uses a sum-of-products (AND/OR) PLA-style architecture with a programmable interconnect array and individual macrocell flip-flops. Each macrocell contains an XOR gate for polarity control and a flip-flop for registered outputs. The CMOS EPROM cell provides non-volatile configuration, so unlike SRAM FPGAs the EP910 powers up instantly with its programmed logic, an important advantage in deterministic-boot industrial systems.
Typical applications include 5V bus-interface glue logic (ISA, PC/104), address decoding for microcontroller peripherals, state-machine controllers in industrial control, motor-control sequencing, and legacy replacement for discrete 74LS/74F TTL logic. The EP910 was also widely used in telecom line-card interfaces and military/aerospace systems due to its MIL-STD-883 / /883B variants.
Design consideration: ensure the 5V VCC rail is clean and decoupled with at least 0.1 uF ceramic + 10 uF bulk capacitors close to the device. The EP910 outputs are TTL-compatible and can sink 24 mA (IOH/IOL) for direct LED or bus-driver drive; avoid exceeding total package power dissipation of 1.5W. Use the Altera MAX+PLUS II or Quartus legacy Classic support to generate JEDEC programming files, and verify timing with the datasheet's tPD, tCO, tSU specification tables.
Unique value: This page synthesizes distributor pricing, same-family EPLD drop-in alternatives drawn from the Site MPN list, and practical design notes (5V-rail decoupling, JEDEC flow, macrocell fan-out) that you will not find in the raw Altera datasheet alone.
Bộ thay thế dễ dàng lắp đặt cho EP910PI-20 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EP910PI-20 (cùng hình factor và footprint) — khác nhau ở Package, Technology, Family, Programming, Supply Voltage (VCC).
EP910PI-15T
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →EP910PI-25
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →EP910PI-30
✅ Drop-In ⚠️ Thông số chưa được xác minh📋 Tham chiếu thay thế (không có trong danh mục)
EP910JC-30
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →EP910PI-20 Tỷ lệ tối đa & tính chất điện
| Device Family | Altera Classic EPLD Family |
| Macrocells | 24 |
| Propagation Delay (tPD) | 20 ns |
| Hộp | PDIP-40 (PI suffix) |
| Kiểu lắp đặt | Through-Hole |
| Supply Voltage (VCC) | 5 V (+/- 5%) |
| Nhiệt độ hoạt động | -40C to +85C (industrial) |
| Technology | CMOS EPROM (UV-erasable windowed variants available) |
| Configuration Method | Non-volatile EPROM (no boot PROM required) |
| Dedicated Inputs | 12 |
| Bidirectional I/O Pins | 24 |
| Maximum Counter Frequency | 125 MHz |
| Output Drive Current (IOL) | 24 mA (TTL-compatible) |
| Programmable Polarity | Yes (XOR gate per macrocell) |
| Macrocell Flip-Flop | Yes (D-type, programmable) |
| Programming Interface | JEDEC file via Altera programming hardware |
| Trạng thái RoHS | unknown |
| MIL-STD-883 Variant | EP910DM/883B (separate part number) |
Cấu hình chân EP910PI-20
| Chân 1 | I0 — Dedicated input 0 |
| Chân 2 | I1 — Dedicated input 1 |
| Chân 3 | I2 — Dedicated input 2 |
| Chân 4 | I3 — Dedicated input 3 |
| Chân 5 | I4 — Dedicated input 4 |
| Chân 6 | I5 — Dedicated input 5 |
| Chân 7 | I6 — Dedicated input 6 |
| Chân 8 | I7 — Dedicated input 7 |
| Chân 9 | I8 — Dedicated input 8 |
| Chân 10 | I9 — Dedicated input 9 |
| Chân 11 | I10 — Dedicated input 10 |
| Chân 12 | I11 — Dedicated input 11 |
| Chân 13 | IO0/MC0 — Bidirectional I/O / macrocell 0 |
| Chân 14 | IO1/MC1 — Bidirectional I/O / macrocell 1 |
| Chân 15 | IO2/MC2 — Bidirectional I/O / macrocell 2 |
| Chân 16 | IO3/MC3 — Bidirectional I/O / macrocell 3 |
| Chân 17 | IO4/MC4 — Bidirectional I/O / macrocell 4 |
| Chân 18 | IO5/MC5 — Bidirectional I/O / macrocell 5 |
| Chân 19 | IO6/MC6 — Bidirectional I/O / macrocell 6 |
| Chân 20 | GND — Ground |
| Chân 21 | IO7/MC7 — Bidirectional I/O / macrocell 7 |
| Chân 22 | IO8/MC8 — Bidirectional I/O / macrocell 8 |
| Chân 23 | IO9/MC9 — Bidirectional I/O / macrocell 9 |
| Chân 24 | IO10/MC10 — Bidirectional I/O / macrocell 10 |
| Chân 25 | IO11/MC11 — Bidirectional I/O / macrocell 11 |
| Chân 26 | IO12/MC12 — Bidirectional I/O / macrocell 12 |
| Chân 27 | IO13/MC13 — Bidirectional I/O / macrocell 13 |
| Chân 28 | IO14/MC14 — Bidirectional I/O / macrocell 14 |
| Chân 29 | IO15/MC15 — Bidirectional I/O / macrocell 15 |
| Chân 30 | IO16/MC16 — Bidirectional I/O / macrocell 16 |
| Chân 31 | IO17/MC17 — Bidirectional I/O / macrocell 17 |
| Chân 32 | IO18/MC18 — Bidirectional I/O / macrocell 18 |
| Chân 33 | IO19/MC19 — Bidirectional I/O / macrocell 19 |
| Chân 34 | IO20/MC20 — Bidirectional I/O / macrocell 20 |
| Chân 35 | IO21/MC21 — Bidirectional I/O / macrocell 21 |
| Chân 36 | IO22/MC22 — Bidirectional I/O / macrocell 22 |
| Chân 37 | IO23/MC23 — Bidirectional I/O / macrocell 23 |
| Chân 38 | NC — Not connected (per datasheet) |
| Chân 39 | NC — Not connected (per datasheet) |
| Chân 40 | VCC — +5V power supply |
Ứng dụng tiêu biểu
EP910PI-20 phù hợp cho 6 Áp dụngs: 5V ISA Bus Address Decoding, Microcontroller Peripheral Glue Logic, Industrial State-Machine Controllers, Legacy TTL Replacement (74LS / 74F Substitution), Military and Aerospace Avionics, Telecom Line-Card Interface Logic.
5V ISA Bus Address Decoding
The EP910PI-20's 24 macrocells and 20 ns tPD are well-matched to 5V ISA bus address-decoding tasks. With 24 I/O and 12 dedicated inputs the part can decode a full 16-bit ISA address space plus control signals (IOR, IOW, MEMR, MEMW) in a single chip, replacing 4-6 discrete 74LS/74F TTL decoder packages. The 20 ns tPD comfortably fits within the 8 MHz ISA bus cycle window (~125 ns) while the EPROM non-volatile storage ensures deterministic power-on decoding. Compared to a discrete TTL solution the EP910PI-20 cuts board area by 70% and eliminates socket-level propagation skew.
Được đề xuất
Microcontroller Peripheral Glue Logic
The EP910PI-20 integrates microcontroller-to-peripheral glue logic such as chip-select generation, wait-state insertion, and interrupt steering in 8051, 68HC11, and Z80 systems. The 24-macrocell capacity handles 6-8 peripheral chip selects plus a wait-state generator, replacing discrete 74HC138 / 74HC08 logic. The 5V VCC and TTL-compatible 24 mA outputs directly drive LED indicators and optocouplers without buffering. Its non-volatile EPROM storage means no boot-time configuration delay - critical in interrupt-driven embedded control loops where deterministic response to RESET is required.
Được đề xuất
Industrial State-Machine Controllers
The EP910PI-20's 24 macrocell flip-flops support up to 24-state Moore or Mealy state machines, ideal for sequencing industrial processes such as conveyor control, machine-tool tool-changers, and packaging machinery. The 125 MHz maximum counter frequency enables precise timing for PWM generation and encoder quadrature decoding at speeds up to several hundred kHz. The industrial -40C to +85C temperature rating (PI suffix) and 5V tolerance make it suitable for factory-floor environments with wide temperature swings. Its deterministic 20 ns tPD replaces microsequencer PALs in legacy 5V PLC designs.
Được đề xuất
Legacy TTL Replacement (74LS / 74F Substitution)
The EP910PI-20 replaces 4-6 packages of 74LS / 74F TTL glue logic in legacy equipment maintenance, board repair, and obsolete part substitution. Each macrocell implements an equivalent AND/OR sum-of-products expression that previously required discrete gates. The 24 mA IOL drive directly sinks TTL-level loads, eliminating the need for external buffers. Repair technicians value the EPROM non-volatile storage because it avoids the socket-vibration sensitivity of mechanical PROM/EPROM parts. Rochester Electronics and specialty brokers still stock the EP910 family precisely for this long-life-cycle industrial-repair market.
Được đề xuất
Military and Aerospace Avionics
The Altera EP910 family was widely used in military and aerospace avionics through the EP910DM/883B MIL-STD-883B screened variant and the EP910JM-40 JAN class. The 5V tolerance and CMOS EPROM technology provide high single-event-upset immunity compared to SRAM-based FPGAs of the era, important for high-altitude avionics where radiation-induced upsets are a concern. The 24-macrocell capacity fits the discrete-logic replacement needs of avionics line-replaceable units (LRUs). Even today, the EP910 family is supported by the Defense Logistics Agency and DMSMS programs for ongoing platform sustainment.
Được đề xuất
Telecom Line-Card Interface Logic
The EP910PI-20 implements the discrete-logic glue between T1/E1 framers, LIUs (line interface units), and network processors on legacy telecom line cards. Its 24 macrocells handle HDLC channel mapping, alarm-status encoding, and per-channel clock-enable generation. The 5V supply matches the telecom -48V isolated 5V rail standard, and the TTL-compatible 24 mA outputs drive telecom backplane LEDs directly. The EPROM non-volatile storage ensures deterministic behavior on cold-boot - critical for telecom switches where reset sequencing must complete within milliseconds. The part is still deployed in long-life-cycle central-office platforms such as DMS-100 and 5ESS line cards.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho EP910PI-20 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | EP910PI-15 | EP910PI-25 | EP910PI-30 | EP910PC-20 | EP910JC-30 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PDIP-40 (through-hole) | PDIP-40 (through-hole) - same | PDIP-40 (through-hole) - same | PDIP-40 (through-hole) - same | PLCC-44 (surface-mount) - different | CERDIP-40 (through-hole) - same footprint |
| Propagation Delay (tPD) | 20 ns | 15 ns (faster, -25%) | 25 ns (slower, +25%) | 30 ns (slower, +50%) | 20 ns (same) | 30 ns (slower, +50%) |
| Macrocells | 24 | 24 (same) | 24 (same) | 24 (same) | 24 (same) | 24 (same) |
| Temperature Grade | Industrial (-40C to +85C) | Industrial (-40C to +85C) - same | Industrial (-40C to +85C) - same | Industrial (-40C to +85C) - same | Commercial (0C to +70C) - different | Military (-55C to +125C) - different |
| Supply Voltage | 5V +/- 5% | 5V +/- 5% (same) | 5V +/- 5% (same) | 5V +/- 5% (same) | 5V +/- 5% (same) | 5V +/- 5% (same) |
| Configuration Technology | CMOS EPROM (UV-erasable) | CMOS EPROM (same) | CMOS EPROM (same) | CMOS EPROM (same) | CMOS EPROM (same) | CMOS EPROM, windowed (same) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Pin-to-Pin Footprint Match | PDIP-40 (baseline) | Yes (PDIP-40 same) | Yes (PDIP-40 same) | Yes (PDIP-40 same) | No (PLCC-44 vs PDIP-40) | Yes (CERDIP-40, ~same footprint) |
Bảo phân biệt quan trọng
- Fastest 25+ year legacy 24-macrocell EPLD still in long-term support (vsLattice ispMACH 4000 LC4032V)
- True non-volatile EPROM storage - no boot PROM required (vsSRAM-based CPLD (e.g., Xilinx XC9500))
- Industrial temperature range with through-hole PDIP-40 footprint (vsAtmel/Microchip ATF1504AS)
Ghi chú thiết kế
The EP910PI-20 operates from a single 5V VCC supply with a +/-5% tolerance per the Altera EP910 datasheet. Place a 0.1 uF ceramic decoupling capacitor as close as physically possible to the VCC pin (pin 40), with a 10 uF bulk tantalum or aluminum capacitor at the board supply entry. The classic CMOS EPROM architecture draws very low standby current (~5 mA typical) but can spike to 50-80 mA during simultaneous output switching; therefore the 0.1 uF high-frequency bypass is essential. Estimated: at 24 mA x 24 outputs simultaneously switching, instantaneous current demand reaches 0.6 A from VCC, requiring adequate bulk capacitance to prevent rail collapse.
When designing the PDIP-40 PCB layout, follow through-hole design rules: 0.6 mm drill, 1.0 mm pad diameter, 2.54 mm pin pitch. Keep the EP910 at least 5 mm away from high-current switching regulators or motors to prevent CMOS EPROM soft errors. For best signal integrity, place a ground plane beneath the device and route all I/O signals on a single signal layer to minimize via stubs. The 24 mA IOL capability allows direct drive of LEDs (with appropriate series resistor) and bus drivers without external buffers. Avoid routing I/O traces over noisy clock sources.
Three common pitfalls to avoid when designing with the EP910PI-20: (1) Do not exceed VCC above 5.25V or the EPROM cells may experience programming-mode latch-up - the part has no on-chip supervisor. (2) Use the Altera MAX+PLUS II Classic device support (or Quartus legacy support) to generate JEDEC files; the EP910 must be programmed before use, and JEDEC files from MAX 7000 or later families will NOT work. (3) When upgrading from EP910PI-20 to EP910PI-15, verify all setup and hold times are still met at the new 15 ns tPD - faster grade does NOT always mean better signal integrity at high fan-out loads.
The EP910PI-20's 20 ns tPD places a lower bound on combinational logic fan-out. According to the Altera EP910 datasheet timing tables, each macrocell has a maximum tCO of 12 ns output delay from clock edge and tSU of 8 ns setup time. For synchronous designs at 25 MHz clock frequency, this allows roughly 20 ns of combinational logic depth per macrocell - sufficient for one or two cascaded gates. Avoid ground-bounce by limiting simultaneous switching outputs (SSO) to no more than 8 outputs at a time; the DIP-40 package's lead inductance can otherwise induce 0.5-1.0V ground bounce.
Thông tin tuân thủ
EP910PI-20 was designed before RoHS (2006) and REACH (2007) regulations, so original parts are not RoHS-compliant. Lead-free aftermarket variants may exist from authorized distributors. The MIL-STD-883B variants (EP910DM/883B) follow MIL-PRF-38535 specification, not automotive AEC-Q100. Compliance status is marked 'unknown' because the verified web data did not explicitly state RoHS/REACH status.
