EP910DM-40 - 24-Macrocell UV EPLD Classic PAL-Type | Altera
MPN: EP910DM-40 ✗ Cuối đờiEP910DM-40 Tóm tắt
A UV Erasable Programmable Logic Device (EPLD) is a type of programmable logic IC that uses ultraviolet light to erase its configuration before re-programming. EPLDs belong to the broader category of Programmable Logic Devices (PLDs) within the programmable logic semiconductor hierarchy: PLD -> EPLD -> Classic EPLD. The EP910 sits between simpler PAL/GAL devices (typically 8-16 macrocells) and larger CPLDs, providing a balance of logic density and predictable timing. Its PAL-type AND/OR architecture with a global bus provides deterministic pin-to-pin delays, which is why EPLDs remained popular for asynchronous state machines and bus-interface glue logic long after FPGAs became mainstream.
Key features include 24 macrocells with user-configurable I/O, a non-volatile UV-erasable configuration memory, 4 dedicated clock inputs supporting two clock domains, and JEDEC-standard fuse-map programming. The EP910DM-40's 40 ns tPD makes it appropriate for control logic running at clock rates up to approximately 20-25 MHz, and its CMOS technology delivers low standby power for always-on systems.
Typical applications include address decoding and bus-interface glue logic for microprocessors, asynchronous state machines, custom decoder/replacement logic, and legacy 5V industrial control boards. The DIP-40 ceramic package (windowed Cerdip) allows in-circuit reprogramming via UV erasure, which is valuable for prototyping and field-upgradable equipment.
When designing with the EP910DM-40, note that 5V CMOS signal levels are mandatory and that unused I/O pins should be left unconnected or tied per datasheet recommendations. The ceramic DIP-40 (windowed) package retains its UV window for re-erasure, while the plastic OTP variants cannot be re-programmed.
This page synthesizes distributor availability, parametric datasheet figures, and Altera EP910 cross-family variant listings that go beyond the standalone EP910 datasheet, helping engineers source and substitute this legacy Classic EPLD part.
Bộ thay thế dễ dàng lắp đặt cho EP910DM-40 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EP910DM-40 (cùng hình factor và footprint) — khác nhau ở Package, Family, Operating Temperature, Programming Method, Supply Voltage (VCC).
EP910DC-40
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910DM-35
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
EP910DC-35
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910DC-30
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910DI-35
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910DI-30
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910DM-40 Tỷ lệ tối đa & tính chất điện
| Product Type | UV Erasable Programmable Logic Device (EPLD) |
| Family | Altera Classic EP910 |
| Architecture | PAL-type AND/OR with global programmable interconnect bus |
| Macrocells | 24 |
| Dedicated Inputs | 36 |
| Dedicated Outputs | 24 |
| Bidirectional I/O Lines | 24 |
| Product Terms | 240 |
| Propagation Delay (tPD) | 40 ns |
| External Clocks | 2 |
| Process Technology | CMOS |
| Hộp | 40-pin Ceramic DIP (Cerdip) with UV window |
| Kiểu lắp đặt | Through-Hole (DIP) |
| Điện áp cung cấp | 5 V |
| Programming Interface | JEDEC-standard fuse-map / UV erasure |
Cấu hình chân EP910DM-40
| Chân 1 | I/O — Bidirectional I/O pin (macrocell 24 I/O bank) |
| Chân 2 | I/O — Bidirectional I/O pin |
| Chân 3 | I/O — Bidirectional I/O pin |
| Chân 4 | I/O — Bidirectional I/O pin |
| Chân 5 | I/O — Bidirectional I/O pin |
| Chân 6 | I/O — Bidirectional I/O pin |
| Chân 7 | I/O — Bidirectional I/O pin |
| Chân 8 | I/O — Bidirectional I/O pin |
| Chân 9 | I/O — Bidirectional I/O pin |
| Chân 10 | I/O — Bidirectional I/O pin |
| Chân 11 | I/O — Bidirectional I/O pin |
| Chân 12 | I/O — Bidirectional I/O pin |
| Chân 13 | I/O — Bidirectional I/O pin |
| Chân 14 | I/O — Bidirectional I/O pin |
| Chân 15 | I/O — Bidirectional I/O pin |
| Chân 16 | I/O — Bidirectional I/O pin |
| Chân 17 | I/O — Bidirectional I/O pin |
| Chân 18 | I/O — Bidirectional I/O pin |
| Chân 19 | I/O — Bidirectional I/O pin |
| Chân 20 | I/O — Bidirectional I/O pin |
| Chân 21 | I/O — Bidirectional I/O pin |
| Chân 22 | I/O — Bidirectional I/O pin |
| Chân 23 | I/O — Bidirectional I/O pin |
| Chân 24 | I/O — Bidirectional I/O pin |
| Chân 25 | IN — Dedicated input pin |
| Chân 26 | IN — Dedicated input pin |
| Chân 27 | IN — Dedicated input pin |
| Chân 28 | IN — Dedicated input pin |
| Chân 29 | IN — Dedicated input pin |
| Chân 30 | IN — Dedicated input pin |
| Chân 31 | IN — Dedicated input pin |
| Chân 32 | IN — Dedicated input pin |
| Chân 33 | IN — Dedicated input pin |
| Chân 34 | IN — Dedicated input pin |
| Chân 35 | IN — Dedicated input pin |
| Chân 36 | IN — Dedicated input pin |
| Chân 37 | CLK — External clock input 1 |
| Chân 38 | CLK — External clock input 2 |
| Chân 39 | VCC — +5V supply |
| Chân 40 | GND — Ground |
Ứng dụng tiêu biểu
EP910DM-40 phù hợp cho 6 Áp dụngs: Microprocessor Bus Interface Glue Logic, Address Decoding and Chip-Select Generation, Asynchronous State Machines, Legacy 5V Industrial Control Boards, Custom Decoder and Logic Replacement, Prototype and Field-Programmable Logic Development.
Microprocessor Bus Interface Glue Logic
The EP910DM-40 is a natural fit for microprocessor bus-interface glue logic where deterministic timing and 5V CMOS signal levels matter. Its 24 dedicated inputs can decode a full 24-bit address bus in a single device, while the 24 dedicated outputs drive chip-select and control signals to peripheral devices. With 40 ns tPD the part fits ISA bus timings (8 MHz) and most 8086/68000 wait-state insertions, and its PAL-type AND/OR architecture guarantees fixed pin-to-pin delay across all I/O - critical for asynchronous bus protocols. The DIP-40 ceramic package supports UV erasure, making it ideal for prototype iterations of board logic before committing to a production mask.
Được đề xuất
Address Decoding and Chip-Select Generation
With 36 dedicated inputs and 240 product terms, the EP910DM-40 can decode complex memory and I/O address ranges without external gates. Each macrocell supports wide OR-terms, allowing full-address decoders for 24-bit address buses plus chip-selects for RAM, ROM, and peripherals. The 40 ns propagation delay is more than adequate for 8-bit and 16-bit microprocessor systems where address valid-to-chip-select propagation must occur in one clock cycle. Designers can implement boot-ROM, peripheral, and memory-mapped I/O chip-selects in one EPLD, replacing 4-6 standard 74LS/HC decoder packages.
Được đề xuất
Asynchronous State Machines
The EP910DM-40's PAL-type architecture with deterministic pin-to-pin delays makes it ideal for asynchronous state machines where setup/hold timing across multiple feedback paths must be guaranteed. Its 24 macrocells can implement 16-24 states with full Mealy or Moore encoding, while the 240 product terms handle wide input combinations. EPLDs outperform early FPGAs in asynchronous designs because their AND-OR plane is fully combinatorial, avoiding the routing-induced variable delays that plague LUT-based FPGAs in pure-async applications. Common uses include protocol converters, bus-arbiters, and industrial sequencers.
Được đề xuất
Legacy 5V Industrial Control Boards
Many legacy industrial control systems designed in the late 1980s and 1990s use the EP910DM-40 for I/O expansion, signal conditioning, and sensor multiplexing in 5V CMOS logic environments. The DIP-40 ceramic package is field-replaceable on through-hole PCBs without rework, and UV erasure allows field firmware updates for long-life industrial equipment. With 24 bidirectional I/O lines and 4 clock inputs supporting two clock domains, the EP910DM-40 can synchronize sensor inputs, drive relay boards, and coordinate stepper-motor control pulses - all in one device. Its CMOS low standby current suits always-on control panels.
Được đề xuất
Custom Decoder and Logic Replacement
The EP910DM-40 is widely used to replace discrete 74LS/74HC logic packages with custom decoders, multiplexers, and combinational glue. Each macrocell replaces 1-3 discrete SSI/MSI packages, and 24 macrocells in one DIP-40 can compress an entire board of small logic into a single socketed part - reducing board area, improving reliability, and simplifying BOM. This application is especially valuable in legacy aerospace, defense, and medical equipment where the exact discrete-logic design must be retained but the BOM must be modernized. UV erasability allows iterative design without scrapping ceramic parts.
Được đề xuất
Prototype and Field-Programmable Logic Development
The EP910DM-40's UV-erasable ceramic windowed package makes it the device of choice for prototyping and iterative development. Engineers can program a JEDEC fuse-map, test it in-circuit, and re-erase with a UV eraser in 20-30 minutes - perfect for early-stage development of glue logic before committing to a one-time-programmable or mask-programmed part. The DIP-40 ceramic package also supports field firmware updates in deployed equipment, making the EP910DM-40 valuable for long-life-cycle products where in-system ISP is not available. Common uses include military, aerospace, and instrumentation prototypes.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho EP910DM-40 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | EP910DC-40 | EP910DM-35 | EP910DC-35 | EP910DC-30 | EP910DI-35 |
|---|---|---|---|---|---|---|
| Package | 40-pin Ceramic DIP (Cerdip) UV | 40-pin Plastic DIP OTP | 40-pin Ceramic DIP (Cerdip) UV | 40-pin Plastic DIP OTP | 40-pin Plastic DIP OTP | 40-pin Ceramic DIP (Cerdip) UV |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Propagation Delay (tPD) | 40 ns | 40 ns | 35 ns | 35 ns | 30 ns | 35 ns |
| Dedicated Inputs | 36 | 36 | 36 | 36 | 36 | 36 |
| Dedicated Outputs | 24 | 24 | 24 | 24 | 24 | 24 |
| Product Terms | 240 | 240 | 240 | 240 | 240 | 240 |
| Erasure Method | UV (windowed) | OTP (one-time programmable) | UV (windowed) | OTP (one-time programmable) | OTP (one-time programmable) | UV (windowed) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Bảo phân biệt quan trọng
- UV-erasable ceramic windowed package for in-circuit reprogramming (vsEP910DC-40)
- 24 macrocells with deterministic PAL-type timing (vsEP610 family (16 macrocells))
- 36 dedicated inputs supporting full 24-bit address decoding (vsGeneric 22V10 PAL (12 dedicated inputs))
Ghi chú thiết kế
When substituting an EP910DM-40 with an EP910DC-40 in an existing design, verify that the application's timing budget tolerates the plastic OTP package's slightly higher output capacitance compared to the ceramic windowed variant - in high-speed bus designs above 20 MHz, this can add 1-2 ns of edge degradation. Both parts share the same die and pinout, so footprint compatibility is guaranteed; only the erase mechanism (UV vs OTP) and minor AC parameters differ.
For EP910DM-40 designs, place 100 nF decoupling capacitors as close as possible to VCC (pin 39) and GND (pin 40) on a 40-pin DIP-40 footprint. Add a 10 uF bulk tantalum or electrolytic capacitor at the board's power-entry point. Because the EP910DM-40 has 24 bidirectional I/O pins that can switch simultaneously, ground bounce can exceed 0.5 V without proper decoupling - so use a low-inductance ground plane under the DIP socket rather than a single ground trace.
The EP910DM-40's PAL-type AND/OR architecture provides fixed pin-to-pin delays independent of logic placement, which is its main advantage over FPGAs for asynchronous designs. However, asynchronous feedback paths through the macrocell register can still create setup-time violations if the input combinational path exceeds 40 ns - always perform static timing analysis on the JEDEC fuse-map using Altera's legacy MAX+PLUS II software before committing the design. Synchronous designs using both clock inputs (CLK1/CLK2) provide the cleanest timing margins.
Estimated: at 5V VCC, the EP910DM-40 draws approximately 100-200 mA active and 5-20 mA standby, dissipating 0.5-1.0 W. The ceramic DIP-40 package has a theta-JA of approximately 50-60 C/W, giving a junction temperature rise of 25-60 C above ambient. For reliable operation across -40 C to +85 C industrial temperatures, no heatsink is required, but ensure adequate airflow in enclosed industrial enclosures.
Thông tin tuân thủ
EP910DM-40 is a legacy Altera Classic EPLD from the early 1990s. Ceramic DIP-40 packages of this era were typically non-RoHS (tin-lead solder finish) and lack modern environmental certifications. RoHS and REACH status were not stated in the verified data. Not applicable for AEC-Q100 automotive qualification.
