EPM5130WC-2 - 128-Macrocell UV PLD MAX 5000 | Altera CQFP-100
MPN: EPM5130WC-2 ✗ Cuối đờiEPM5130WC-2 Tóm tắt
A Programmable Logic Device (PLD) is a digital integrated circuit whose logic function is defined by the user after manufacture, rather than being hard-wired at the fab. UV-erasable PLDs such as the MAX 5000 family sit within the broader taxonomy of programmable logic devices (PLDs -> CPLD/PLD -> programmable logic -> digital logic IC -> semiconductor). They are commonly positioned between discrete TTL/CMOS glue logic and FPGAs, offering deterministic timing, non-volatile configuration, and predictable pin-to-pin delays with far lower complexity than modern FPGAs.
Key features of the EPM5130WC-2 include 128 macrocells, 45 ns worst-case pin-to-pin propagation delay (tPD), a 0.650 mm terminal pitch gull-wing CQFP-100 ceramic windowed package, single 5V supply operation, and 48 user I/O lines plus 19 dedicated inputs. The MAX 5000 architecture uses EEPROM configuration cells with multi-level AND/OR array logic, providing deterministic combinatorial and registered logic with predictable timing.
The device's CMOS technology and MAX 5000 multi-level AND/OR array deliver high density for a 5V PLD with predictable, deterministic timing. Each macrocell includes a programmable register that can be configured as D, T, JK, or SR flip-flop with independent clock and reset, supporting state-machine and registered-logic designs at speeds suitable for control-plane applications.
Typical applications include 5V logic replacement in legacy industrial control systems, bus-interface glue logic, address decoding for microprocessor systems, state-machine controllers, and prototype development using UV erasure. Designers favor the MAX 5000 family for its deterministic timing and rugged ceramic packaging.
When designing with this device, verify the host PCB's footprint against the 100-terminal CQFP (R-CQFP-G100) land pattern with 0.650 mm pitch. Programming requires a compatible Altera programmer and a MAX+PLUS II or QUARTUS design flow; UV erasure needs a 254 nm UV lamp rated at approximately 25 W·s/cm² integrated dose. Note the part is no longer in active production - plan for last-time-buy or consider MAX 7000/MAX II family successors.
Bộ thay thế dễ dàng lắp đặt cho EPM5130WC-2 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EPM5130WC-2 (cùng hình factor và footprint) — khác nhau ở Process Technology, Package, Supply Voltage (VCC), Configuration Memory, Operating Temperature.
EPM5130WC-1
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM5130WC-1AA
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM5130WC-1
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM5130QC-1
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM5130JC-1
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM5130LC
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM5130WC-2 Tỷ lệ tối đa & tính chất điện
| Device Family | MAX 5000 |
| Product Type | UV-Erasable PLD (CPLD) |
| Macrocell Count | 128 |
| Propagation Delay (tPD) | 45 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V |
| Nhiệt độ hoạt động | 0 °C to 70 °C (Commercial) |
| Process Technology | CMOS |
| Dedicated Inputs | 19 |
| User I/O Lines | 48 |
| Total Inputs (I/O + dedicated) | 68 |
| Package Type | 100-terminal Ceramic CQFP (R-CQFP-G100), windowed, gull-wing |
| Terminal Pitch | 0.650 mm |
| Kiểu lắp đặt | Surface Mount |
| Configuration Memory | UV-erasable CMOS EEPROM cells |
| Speed Grade | -2 (45 ns) |
| Logic Elements | AND/OR array with programmable macrocell register |
Cấu hình chân EPM5130WC-2
| Chân 1 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 2 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 3 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 4 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 5 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 6 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 7 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 8 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 9 | INPUT — Dedicated input pin |
| Chân 10 | INPUT — Dedicated input pin |
| Chân 11 | INPUT — Dedicated input pin |
| Chân 12 | INPUT — Dedicated input pin |
| Chân 13 | INPUT — Dedicated input pin |
| Chân 14 | INPUT — Dedicated input pin |
| Chân 15 | INPUT — Dedicated input pin |
| Chân 16 | INPUT — Dedicated input pin |
| Chân 17 | INPUT — Dedicated input pin |
| Chân 18 | INPUT — Dedicated input pin |
| Chân 19 | INPUT — Dedicated input pin |
| Chân 20 | INPUT — Dedicated input pin |
| Chân 21 | INPUT — Dedicated input pin |
| Chân 22 | INPUT — Dedicated input pin |
| Chân 23 | INPUT — Dedicated input pin |
| Chân 24 | INPUT — Dedicated input pin |
| Chân 25 | INPUT — Dedicated input pin |
| Chân 26 | INPUT — Dedicated input pin |
| Chân 27 | INPUT — Dedicated input pin |
| Chân 28 | GND — Ground |
| Chân 29 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 30 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 31 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 32 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 33 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 34 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 35 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 36 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 37 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 38 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 39 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 40 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 41 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 42 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 43 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 44 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 45 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 46 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 47 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 48 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 49 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 50 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 51 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 52 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 53 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 54 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 55 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 56 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 57 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 58 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 59 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 60 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 61 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 62 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 63 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 64 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 65 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 66 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 67 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 68 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 69 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 70 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 71 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 72 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 73 | GND — Ground |
| Chân 74 | VCC — 5V supply |
| Chân 75 | VCC — 5V supply |
| Chân 76 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 77 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 78 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 79 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 80 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 81 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 82 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 83 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 84 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 85 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 86 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 87 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 88 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 89 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 90 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 91 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 92 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 93 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 94 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 95 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 96 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 97 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 98 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 99 | I/O — Bidirectional I/O pin (macrocell assigned) |
| Chân 100 | I/O — Bidirectional I/O pin (macrocell assigned) |
Ứng dụng tiêu biểu
EPM5130WC-2 phù hợp cho 7 Áp dụngs: Legacy 5V Industrial Control Logic, Microprocessor Bus Interface Glue Logic, State Machine Controllers, Address Decoding for Memory Systems, Aerospace and Defense Avionics (Legacy), Prototype Development and Design Iteration, Telecommunications Backplane Glue Logic.
Legacy 5V Industrial Control Logic
The EPM5130WC-2 is well-suited to legacy 5V industrial control boards that were designed around the original MAX 5000 family. With 128 macrocells and 48 user I/O lines, it replaces multiple 74LS/74HC discrete logic packages with a single programmable device, reducing PCB area and assembly cost. The 45 ns tPD is sufficient for control-plane tasks such as sensor multiplexing, motor-driver sequencing, and interlock logic at cycle times of several hundred nanoseconds. The 5V supply (4.75V–5.25V) matches existing 5V logic rails without level translation. Designers continuing to manufacture or repair legacy industrial systems find the WC-2 invaluable for sustaining equipment with no redesign budget.
Được đề xuất
Microprocessor Bus Interface Glue Logic
With 19 dedicated inputs and 48 I/O lines, the EPM5130WC-2 can implement address decoding, chip-select generation, wait-state insertion, and bus arbitration between a microprocessor and peripherals. The deterministic 45 ns tPD makes it ideal for 8-bit and 16-bit bus cycles such as those used with 8051, 68k, or 8086-family microprocessors. The 100-pin CQFP provides ample I/O for memory-mapped peripherals and DMA control. The UV-erasable window enables rapid prototype iteration during bus-protocol bring-up. For new designs, consider Altera MAX 7000AE with in-system programmability for faster debug cycles.
Được đề xuất
State Machine Controllers
Each EPM5130WC-2 macrocell includes a configurable flip-flop (D, T, JK, or SR) that can implement complex state machines across 128 cells, supporting controllers with 50+ states and combinational outputs. Deterministic 45 ns pin-to-pin delay simplifies worst-case timing analysis for safety-critical or real-time control loops. The 5V supply is compatible with TTL-level inputs, simplifying interface to legacy sensors and actuators. State machines for protocol handlers (UART, SPI bit-banging, custom serial protocols) are a common use case in industrial automation. The ceramic CQFP package provides excellent thermal performance and hermeticity for harsh environments.
Được đề xuất
Address Decoding for Memory Systems
The EPM5130WC-2's 128 macrocells and 68 inputs provide ample capacity to decode addresses for memory-mapped systems with 16 or 24 address lines. With 45 ns tPD the device fits easily within typical microprocessor memory-access cycles (typically 100–250 ns). The 48 user I/O lines drive multiple chip-select outputs to SRAM, EPROM, ROM, and peripheral banks. UV-erasable programmability lets designers iterate on address maps quickly during prototype development. The 5V supply integrates seamlessly with TTL and CMOS 5V memory components. For higher-performance systems, the EPM5130WC-1 speed grade (30 ns) is a pin-compatible drop-in on the same PCB.
Được đề xuất
Aerospace and Defense Avionics (Legacy)
The ceramic CQFP-100 (R-CQFP-G100) package of the EPM5130WC-2 provides hermetic sealing and a wide operating temperature tolerance suitable for aerospace and defense applications where Altera MAX 5000 parts were historically qualified. The UV-windowed ceramic package supports reprogramming for design updates during sustainment programs. With 128 macrocells, the device implements control logic, bus interfaces, and signal conditioning for legacy avionics platforms. Note that the EPM5130WC-2 is commercial-grade (0°C to 70°C); for full military temperature range (-55°C to +125°C), consider the EPM5130GM883B / EPM5130GI military variants in the same CQFP-100 footprint.
Được đề xuất
Prototype Development and Design Iteration
The UV-erasable window of the EPM5130WC-2 allows engineers to erase and reprogram the device repeatedly during prototype development, making it well-suited to design iteration cycles. Each erase cycle uses 254 nm UV light at approximately 25 W·s/cm² dose, after which the part is fully reprogrammed via the Altera Logic Programmer using MAX+PLUS II. The 128-macrocell capacity supports substantial logic prototypes in a single chip, allowing designers to evaluate architecture decisions before committing to OTP or one-time-programmable variants. The ceramic CQFP package is robust to repeated handling during development. For production designs without UV erasure, consider one-time-programmable (OTP) variants or migrate to MAX 7000AE with in-system programmability.
Được đề xuất
Telecommunications Backplane Glue Logic
The EPM5130WC-2's 68 inputs and 48 I/O lines support legacy telecommunications backplane designs that require address decoding, clock distribution, and protocol conversion across multiple line cards. The 45 ns tPD is appropriate for backplane speeds in the 10–25 MHz range common in telecom equipment from the 1990s and early 2000s. The 5V supply interfaces directly to TTL-level backplane transceivers. The ceramic CQFP package withstands the thermal cycling of telecom central-office environments. The deterministic timing simplifies worst-case timing analysis required by telecom standards. New designs should consider MAX 7000AE or MAX V CPLDs with 3.3V core and improved I/O support.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho EPM5130WC-2 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | EPM5130WC-1 | EPM5130WC-1AA | EPM5130WC | EPM5130QC-1 |
|---|---|---|---|---|---|
| Package | CQFP-100 (R-CQFP-G100), ceramic windowed | CQFP-100 (R-CQFP-G100) - same | CQFP-100 (R-CQFP-G100) - same | CQFP-100 (R-CQFP-G100) - same | CQFP-100 (R-CQFP-G100) - same |
| Brand | Altera | Altera - same | Altera - same | Altera - same | Altera - same |
| Macrocell Count | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tPD) | 45 ns (-2 speed grade) | 30 ns (-1 speed grade, faster) | 30 ns (-1 speed grade, faster) | unspecified (default grade) | 30 ns (-1 speed grade, faster) |
| Supply Voltage | 4.75V to 5.25V | 4.75V to 5.25V | 4.75V to 5.25V | 4.75V to 5.25V | 4.75V to 5.25V |
| Dedicated Inputs | 19 | 19 | 19 | 19 | 19 |
| User I/O Lines | 48 | 48 | 48 | 48 | 48 |
| Configuration Memory | UV-erasable CMOS EEPROM | UV-erasable CMOS EEPROM | UV-erasable CMOS EEPROM | UV-erasable CMOS EEPROM | UV-erasable CMOS EEPROM |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Operating Temperature | 0°C to 70°C (commercial) | 0°C to 70°C | 0°C to 70°C | 0°C to 70°C | 0°C to 70°C |
Bảo phân biệt quan trọng
- Faster speed grade option in same package (vsEPM5130WC-1)
- UV-erasable window for design iteration (vsEPM5130JC-1 (OTP ceramic))
- High macrocell density for MAX 5000 family (vsEPM5064 (smaller MAX 5000 member))
- Commercial temperature grade at lower cost (vsEPM5130GM883B (military grade))
Ghi chú thiết kế
The EPM5130WC-2 is in obsolete lifecycle status - design new products around MAX 7000AE, MAX II, or MAX V CPLDs with in-system programmability. For sustaining legacy boards, plan a last-time-buy strategy and verify the ceramic CQFP-100 land pattern matches your PCB footprint. The UV-windowed ceramic package requires careful handling; protect the quartz window from scratches and contamination that would block erasure. Programming requires the legacy Altera Logic Programmer (PLE-3 or equivalent) using MAX+PLUS II software - this tool chain is no longer supported by Intel FPGA. New designs should not depend on EPM5130WC-2 availability beyond legacy inventory.
Estimated: at static 5V supply and CMOS quiescent state, the EPM5130WC-2 typically consumes less than 200 mW with all outputs unloaded; output switching adds dynamic current proportional to frequency and load capacitance. The ceramic CQFP-100 package provides excellent thermal conductivity; however, for continuous high-frequency switching (above 25 MHz), verify junction temperature against the 0°C to 70°C commercial range. The hermetic ceramic package is suitable for sealed-environment applications where plastic packages would outgas.
The 100-terminal CQFP (R-CQFP-G100) with 0.650 mm terminal pitch requires a fine-pitch PCB land pattern. Follow Altera's recommended footprint with solder mask defined pads (SMD) for reliable solder joint formation. Place at least one 0.1 µF decoupling capacitor near each VCC pin pair (74, 75) and a bulk 10 µF tantalum or ceramic capacitor on the 5V supply rail. Keep programming pin traces short and isolated from high-speed signal traces to avoid coupling during JTAG/programming operations.
Route dedicated inputs (19 pins) and I/O lines (48 pins) with controlled impedance if switching above 10 MHz; for slower control logic at 1-5 MHz, standard 50 Ω traces are adequate. Keep I/O lines assigned to high-drive outputs physically separated from sensitive input traces. The CQFP package has ground pins at 28 and 73 - connect both to a low-impedance ground plane for supply decoupling and EMI suppression. For UV erasure compatibility, leave the package top window accessible (do not place components or heatsinks directly over the ceramic window).
Thông tin tuân thủ
RoHS, REACH, lead-free, halogen-free, and conflict-mineral compliance status not specified in the provided data. The EPM5130WC-2 is an obsolete commercial-grade ceramic package PLD; lead-free and RoHS compliance is unlikely given the legacy era (introduced ~late 1980s) and ceramic package construction. AEC-Q100 not applicable (this is a programmable logic device, not an automotive-grade analog IC). For verified compliance data, contact Intel FPGA (formerly Altera) directly or check the original MAX 5000 datasheet addendum.
