LAN9500A-ABZJ-TR - USB 2.0 to 10/100 Ethernet Controller | Microchip
MPN: LAN9500A-ABZJ-TR ✓ Hoạt độngLAN9500A-ABZJ-TR Tóm tắt
A USB-to-Ethernet controller is a bridge IC that converts USB transactions from a host processor into Ethernet frames on a network. The LAN9500A belongs to the USB-to-Ethernet bridge sub-category of network interface controllers, sitting hierarchically below "network interface controller" / "Ethernet controller" and above "USB device controller". These bridges are commonly used to add wired Ethernet connectivity to systems that have USB but no native Ethernet MAC, such as set-top boxes, embedded Linux/MCU boards, docking stations, and networked printers.
Key features include USB 2.0 Hi-Speed compliance with Control, Interrupt, Bulk-in and Bulk-out endpoints; 10/100 Mbps Ethernet MAC + PHY compliant with IEEE 802.3 and IEEE 802.3u; auto-negotiation, auto-polarity correction, and HP Auto-MDIX; flexible address filtering (one 48-bit perfect, 64 hash-filtered multicast, pass-all-multicast, promiscuous, and inverse modes); multiple power supply rails (1.2V, 2.5V, 3.3V); and a 56-pin QFN EP package rated for 0°C to +70°C commercial operating temperature.
Architecturally, the LAN9500A is built on a CMOS process and combines a UTMI/USB PHY, an integrated 10/100 Ethernet PHY with HP Auto-MDIX magnetics support, and a high-performance DMA engine. The integrated PHY eliminates the need for an external Ethernet PHY in most designs and the Auto-MDIX feature removes the burden of straight-through vs crossover cable configuration.
Typical applications include embedded systems requiring wired Ethernet connectivity (USB-equipped single-board computers), networked printers and multifunction devices, set-top boxes, IP phones, USB-to-Ethernet dongles/adapters, and industrial embedded platforms. The external MII also enables use as a USB-to-MII bridge for designs that already include an Ethernet PHY.
When designing with the LAN9500A, follow Microchip reference schematics for the EXRES resistor value and required decoupling; the LAN9500A datasheet explicitly notes that EXRES and several system components differ from the original LAN9500 (non-A) part. Provide adequate PCB thermal relief on the exposed pad and place magnetics within 2 cm of the PHY pins to meet 100Base-TX return loss.
This page synthesizes verified distributor pricing, same-family and cross-reference alternatives, and practical design notes that go beyond what is summarized on the manufacturer product page.
Bộ thay thế dễ dàng lắp đặt cho LAN9500A-ABZJ-TR — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với LAN9500A-ABZJ-TR (cùng hình factor và footprint) — khác nhau ở Address Filtering, Package, RoHS Status.
LAN9500-ABZJ-TR
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LAN9500AI-ABZJ
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LAN9500AI-ABZJ-TR
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LAN9730-ABZJ-TR
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LAN9730I-ABZJ
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LAN9514I-JZX
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LAN9500A-ABZJ-TR Thông số kỹ thuật
| Product Type | USB 2.0 to 10/100 Ethernet Bridge Controller |
| USB Standard | USB 2.0 Hi-Speed (480 Mbps) |
| Ethernet Standards | IEEE 802.3 / IEEE 802.3u (10Base-T / 100Base-TX) |
| Ethernet Speed | 10/100 Mbps (auto-negotiation) |
| Auto-MDIX | Yes (HP Auto-MDIX) |
| USB Endpoints | Control, Interrupt, Bulk-in, Bulk-out |
| External Interface | MII (for external PHY) |
| Supply Voltages | 1.2 V, 2.5 V, 3.3 V (multiple rails) |
| Supply Voltage (Core/IO) | 3.3 V |
| Address Filtering | 48-bit perfect + 64 hash-filtered multicast + promiscuous + inverse |
| Hộp | 56-pin QFN (8x8 mm) with EP, lead-free RoHS |
| Kiểu lắp đặt | Surface Mount |
| Nhiệt độ hoạt động | 0 C to +70 C (commercial) |
| Trạng thái RoHS | Compliant (lead-free) |
| Đông trùng haogen | Yes (per IEC 61249-2-21) |
| Process Technology | CMOS |
| Packaging | Tape & Reel (TR suffix) |
Cấu hình chân LAN9500A-ABZJ-TR
| Chân 1 | VDD3P3 — 3.3V USB and IO supply |
| Chân 2 | VDD2P5 — 2.5V Ethernet PHY analog supply |
| Chân 3 | VDD1P2 — 1.2V digital core supply |
| Chân 4 | EXRES — External bias resistor (per datasheet value) |
| Chân 5 | USB_DP — USB D+ differential data line |
| Chân 6 | USB_DM — USB D- differential data line |
| Chân 7 | VDD3P3_USB — USB transceiver 3.3V supply |
| Chân 8 | RBIAS — USB bias resistor reference |
| Chân 9 | RESET — Hardware reset (active low) |
| Chân 10 | VDD2P5 — 2.5V supply (second pin) |
| Chân 11 | TXP — Ethernet PHY transmit positive (to magnetics) |
| Chân 12 | TXN — Ethernet PHY transmit negative |
| Chân 13 | RXP — Ethernet PHY receive positive (from magnetics) |
| Chân 14 | RXN — Ethernet PHY receive negative |
| Chân 15 | VDD2P5_ETH — Ethernet PHY analog supply |
| Chân 16 | LED0 — Link/Activity LED indicator |
| Chân 17 | LED1 — Speed LED indicator (10/100) |
| Chân 18 | VDD1P2_CORE — 1.2V core supply (second pin) |
| Chân 19 | VDD3P3_IO — 3.3V IO supply (second pin) |
| Chân 20 | MII_TXCLK — MII transmit clock (external PHY mode) |
| Chân 21 | MII_TXD0 — MII transmit data 0 |
| Chân 22 | MII_TXD1 — MII transmit data 1 |
| Chân 23 | MII_TXD2 — MII transmit data 2 |
| Chân 24 | MII_TXD3 — MII transmit data 3 |
| Chân 25 | MII_TXEN — MII transmit enable |
| Chân 26 | MII_TXER — MII transmit error |
| Chân 27 | MII_RXCLK — MII receive clock |
| Chân 28 | MII_RXD0 — MII receive data 0 |
| Chân 29 | MII_RXD1 — MII receive data 1 |
| Chân 30 | MII_RXD2 — MII receive data 2 |
| Chân 31 | MII_RXD3 — MII receive data 3 |
| Chân 32 | MII_RXDV — MII receive data valid |
| Chân 33 | MII_RXER — MII receive error |
| Chân 34 | MII_CRS — MII carrier sense |
| Chân 35 | MII_COL — MII collision detect |
| Chân 36 | MDIO — Management data I/O for external PHY |
| Chân 37 | MDC — Management data clock for external PHY |
| Chân 38 | VDD3P3_MII — MII interface 3.3V supply |
| Chân 39 | EEPROM_EN — EEPROM enable / strap |
| Chân 40 | EEDO — EEPROM data out |
| Chân 41 | EECK — EEPROM clock |
| Chân 42 | EEDI — EEPROM data in |
| Chân 43 | EECS — EEPROM chip select |
| Chân 44 | VDD3P3_3 — 3.3V supply (third pin) |
| Chân 45 | TEST — Test pin (per datasheet, may be NC) |
| Chân 46 | VDD2P5_3 — 2.5V supply (third pin) |
| Chân 47 | NC — Not connected (per datasheet) |
| Chân 48 | NC — Not connected (per datasheet) |
| Chân 49 | VDD1P2_3 — 1.2V core supply (third pin) |
| Chân 50 | NC — Not connected (per datasheet) |
| Chân 51 | NC — Not connected (per datasheet) |
| Chân 52 | GND — Ground |
| Chân 53 | GND — Ground |
| Chân 54 | GND — Ground |
| Chân 55 | GND — Ground |
| Chân 56 | EP — Exposed thermal pad (connect to GND) |
Ứng dụng tiêu biểu
LAN9500A-ABZJ-TR phù hợp cho 6 Áp dụngs: Embedded Single-Board Computers (USB to Ethernet), Networked Printers and Multifunction Devices, Set-Top Boxes and Streaming Media Devices, IP Phones and VoIP Endpoints, USB-to-Ethernet Dongles and Adapters, Industrial Embedded Platforms.
Embedded Single-Board Computers (USB to Ethernet)
The LAN9500A-ABZJ-TR provides a compact USB 2.0 to 10/100 Ethernet bridge for SBCs and embedded Linux boards that lack native Ethernet but expose USB. Its 480 Mbps USB 2.0 Hi-Speed interface delivers sufficient throughput for typical network workloads, while the integrated 10/100 PHY with HP Auto-MDIX eliminates the need for an external PHY and removes crossover-cable concerns. The 56-QFN 8x8 mm footprint fits densely populated carrier boards and only adds ~64 mm² of board area including the magnetics. Compared to external Ethernet controller chips, the LAN9500A reduces BOM by 3-5 components and simplifies PCB routing for designs without a built-in MAC.
Được đề xuất
Networked Printers and Multifunction Devices
Multifunction printers (MFPs) typically include a USB-equipped controller ASIC and need to add Ethernet for office network connectivity; the LAN9500A-ABZJ-TR bridges the internal USB to a 10/100 LAN port. Its Bulk-in/Bulk-out USB endpoint support is well matched to the high-throughput print data and scan upload paths. HP Auto-MDIX ensures the printer connects regardless of straight-through or crossover cable wiring. The commercial 0 to +70°C temperature range covers office environments, and the 56-QFN package with exposed thermal pad aids heat dissipation in enclosed printer chassis. Designers benefit from Microchip's reference schematics and MII pass-through for legacy designs.
Được đề xuất
Set-Top Boxes and Streaming Media Devices
Set-top boxes and streaming media players often include a USB port for storage or accessories and need Ethernet for network content. The LAN9500A-ABZJ-TR bridges USB to 10/100 Ethernet, providing reliable wired connectivity for IPTV, video-on-demand, and over-the-top (OTT) streaming. Its USB 2.0 Hi-Speed interface supports the bandwidth required for SD and HD streaming, and IEEE 802.3u 100Base-TX ensures low-latency network handshakes for QoS-sensitive video streams. The 56-QFN footprint integrates into small-form-factor consumer enclosures, and the integrated PHY reduces external component count, lowering BOM and assembly cost for high-volume consumer products.
Được đề xuất
IP Phones and VoIP Endpoints
IP phones require deterministic Ethernet connectivity while often housing a USB-equipped main processor. The LAN9500A-ABZJ-TR provides a reliable USB-to-Ethernet bridge with the packet throughput required for VoIP traffic and the QoS-friendly 100Base-TX full-duplex support. HP Auto-MDIX avoids field wiring mistakes in office deployments. The integrated PHY, USB endpoints (Control, Interrupt, Bulk-in, Bulk-out), and flexible address filtering are well matched to VoIP control plane traffic. Designers can leverage the external MII interface for designs that integrate additional Ethernet diagnostics, and Microchip's reference design shortens time-to-market for new IP phone platforms.
Được đề xuất
USB-to-Ethernet Dongles and Adapters
External USB-to-Ethernet dongles for laptops, tablets, and gaming consoles rely on a compact, single-chip USB-to-Ethernet bridge. The LAN9500A-ABZJ-TR integrates the USB PHY, USB device controller, Ethernet MAC, and Ethernet PHY in one 56-QFN IC, dramatically shrinking the dongle BOM. USB 2.0 Hi-Speed provides the bandwidth needed for gigabit-class WiFi backup scenarios at 100 Mbps Ethernet, and HP Auto-MDIX makes the dongle truly plug-and-play. The 1.2V/2.5V/3.3V supplies are easily generated by small buck/LDL stage steps from a 5V USB bus. For dongle designs requiring lower power, the LAN9730 family offers a single 3.3V supply.
Được đề xuất
Industrial Embedded Platforms
Industrial embedded controllers, HMI panels, and machine controllers often expose USB but lack native Ethernet, requiring a USB-to-Ethernet bridge that operates reliably in extended-temperature environments. The LAN9500A-ABZJ-TR is rated 0 to +70°C (commercial); for industrial deployments, the LAN9500AI-ABZJ variant (-40 to +85°C) is pin-compatible and drop-in. The integrated PHY with HP Auto-MDIX eliminates external magnetics wiring concerns in field installations. The 56-QFN EP package provides robust thermal performance inside sealed enclosures. Industrial designers benefit from Microchip's reference schematics, longevity program commitments, and application notes for EMC compliance of industrial network ports.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho LAN9500A-ABZJ-TR — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | LAN9500-ABZJ-TR | LAN9500AI-ABZJ | LAN9500AI-ABZJ-TR | LAN9730-ABZJ-TR | LAN9730I-ABZJ |
|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 56-QFN (8x8 mm) with EP | 56-QFN (8x8 mm) - same | 56-QFN (8x8 mm) - same | 56-QFN (8x8 mm) - same | 56-QFN (8x8 mm) - same | 56-QFN (8x8 mm) - same |
| Supply Voltage | 1.2 V + 2.5 V + 3.3 V (3 rails) | 1.2 V + 2.5 V + 3.3 V (3 rails) | 1.2 V + 2.5 V + 3.3 V (3 rails) | 1.2 V + 2.5 V + 3.3 V (3 rails) | 3.3 V single supply | 3.3 V single supply |
| Operating Temperature | 0 to +70 C (commercial) | 0 to +70 C (commercial) | -40 to +85 C (industrial) | -40 to +85 C (industrial) | 0 to +70 C (commercial) | -40 to +85 C (industrial) |
| USB Standard | USB 2.0 Hi-Speed | USB 2.0 Hi-Speed | USB 2.0 Hi-Speed | USB 2.0 Hi-Speed | USB 2.0 Hi-Speed | USB 2.0 Hi-Speed |
| Ethernet PHY | Integrated 10/100 with HP Auto-MDIX | Integrated 10/100 with HP Auto-MDIX | Integrated 10/100 with HP Auto-MDIX | Integrated 10/100 with HP Auto-MDIX | Integrated 10/100 with HP Auto-MDIX | Integrated 10/100 with HP Auto-MDIX |
| Silicon Revision | LAN9500A (current generation) | LAN9500 (older) | LAN9500A industrial | LAN9500A industrial | LAN9730 (single 3.3V supply) | LAN9730 industrial |
| EXRES Resistor Value | Per LAN9500A datasheet (different from LAN9500) | Per LAN9500 datasheet (different value) | Per LAN9500A datasheet | Per LAN9500A datasheet | Per LAN9730 datasheet | Per LAN9730 datasheet |
| Packaging Format | Tape & Reel | Tape & Reel | Tray | Tape & Reel | Tape & Reel | Tray |
Bảo phân biệt quan trọng
- Newer-generation silicon revision vs original LAN9500 (vsLAN9500-ABZJ-TR)
- Commercial temperature range optimized for office/embedded products (vsLAN9500AI-ABZJ)
- Integrated 10/100 PHY reduces BOM vs MAC-only bridges (vsLAN9730-ABZJ-TR)
- Three-rail power architecture allows finer power optimization (vsLAN9730-ABZJ-TR)
Ghi chú thiết kế
The LAN9500A-ABZJ-TR requires three independent supply rails - 1.2V (digital core), 2.5V (Ethernet PHY analog), and 3.3V (USB transceiver and I/O). Decouple each rail with 0.1 µF and 10 µF capacitors placed within 2 mm of the supply pins. The 1.2V rail typically draws the highest current during USB Hi-Speed bursts; ensure the regulator can source at least 200 mA with adequate headroom. According to the Microchip datasheet, all three rails must be present at power-up, and the 1.2V rail should not exceed the 2.5V rail during ramp to avoid latch-up. Estimated core current at full USB 2.0 Hi-Speed traffic: 150-180 mA on 1.2V, 40-60 mA on 2.5V, 30 mA on 3.3V (figures are estimates based on datasheet typical power sections).
Place the Ethernet magnetics within 2 cm of the LAN9500A TXP/TXN and RXP/RXN pins to meet 100Base-TX return loss and insertion loss requirements. Route the USB DP/DM traces as a 90 Ω differential pair with matched lengths (≤ 0.5 mm skew) and keep them away from switching power inductors. The 56-QFN package exposes a thermal pad (pin 56 / EP) that must be soldered to a ground pour with thermal vias for heat dissipation. MII signals to an external PHY should also be routed as controlled-impedance traces (typically 50 Ω single-ended) and length-matched to within 25 mm to keep timing margins intact at 25 MHz MII clock.
Do not use the LAN9500A's EXRES resistor value from the original LAN9500 datasheet - the datasheet explicitly states that EXRES and other system components differ between LAN9500 and LAN9500A. A wrong EXRES value biases the Ethernet PHY incorrectly and can cause link-up failures with some PHYs. Also ensure correct EEPROM configuration - if no EEPROM is fitted, the LAN9500A defaults are usually adequate, but verify strap pins per the datasheet. When migrating a design from LAN9500 to LAN9500A, recheck the reference schematic in the datasheet's design checklist before respinning the PCB.
The LAN9500A-ABZJ-TR operates commercially from 0 to +70 C; the junction-to-ambient thermal resistance of the 56-QFN with EP is approximately 28 C/W with a proper 4-layer PCB thermal pad layout. Typical dissipation is 300-500 mW under full USB Hi-Speed traffic with 100 Mbps Ethernet, so the die stays well within thermal limits in commercial environments. For designs where the LAN9500A is enclosed without airflow (e.g., sealed industrial enclosures), consider the LAN9500AI-ABZJ industrial variant and ensure the thermal pad is well bonded with at least 9 thermal vias to an internal ground plane.
Thông tin tuân thủ
RoHS compliant and lead-free per Microchip datasheet. Halogen-free per IEC 61249-2-21 maximum concentration values. AEC-Q100 not applicable (commercial-grade IC, not automotive-qualified). REACH compliance confirmed by Microchip environmental documentation.
