LTC2123CUK - 14-Bit 250Msps Dual ADC, JESD204B | ADI
MPN: LTC2123CUK ✓ Hoạt độngLTC2123CUK Tóm tắt
A pipelined ADC is a multi-stage converter that uses low-resolution flash sub-ADCs and a digital correction network to digitize an analog signal at very high sample rates while maintaining fine amplitude resolution. Within the broader converter taxonomy, pipelined ADCs sit between high-speed flash ADCs and lower-power successive-approximation ADCs, and they are the most widely used architecture for sampling rates from ~50 Msps to several hundred Msps. The LTC2123CUK belongs to this high-speed pipelined class and is positioned for multi-lane serial-data transport via the JEDEC-standardized JESD204B serial interface.
Key features include a 14-bit resolution with 250 Msps sample rate, dual simultaneously-sampling analog inputs, an integrated clock and sample-and-hold front end, a 1.25 GHz analog input bandwidth, and a JESD204B-encoded serial data interface that minimizes board-routing complexity. The device operates from standard 1.8 V supply rails and includes internal dithering to improve low-amplitude linearity for small-signal RF work.
The LTC2123CUK architecture uses a multi-stage switched-capacitor pipeline with proprietary calibration that flattens the noise and linearity curves across the Nyquist band. By running at 250 Msps from a single 1.8 V supply, the part achieves an SNR floor (70 dBFS) and SFDR (90 dBFS) that previously required dual-supply 5 V parts. The JESD204B Subclass 1 output supports deterministic latency and up to 4 lanes, which simplifies FPGA/ASIC capture when multiple converters must be phase-coherent.
Typical applications include multi-antenna diversity receivers, IF digitizers for wireless base stations, broadband instrumentation, phased-array radar signal chains, and high-speed data acquisition test systems. The wide input bandwidth allows straightforward sampling of intermediate frequencies in the second or third Nyquist zone.
When designing with the LTC2123CUK, plan the PCB layout for 50 ohm controlled-impedance analog inputs and tightly decouple the two 1.8 V supply domains (analog AVDD and digital DVDD/DRVDD) close to the package. The exposed thermal pad must be soldered to a continuous ground island to keep junction temperature within the commercial 0 to 70 C operating range.
This page synthesizes distributor pricing, drop-in compatible variants from the same LTC2123 family, application context, and practical design notes not collected in any single manufacturer document.
Bộ thay thế dễ dàng lắp đặt cho LTC2123CUK — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với LTC2123CUK (cùng hình factor và footprint) — khác nhau ở Digital Output Interface, Input Type, Lead-Free / Halogen-Free, Operating Temperature Range, RoHS Status.
LTC2123CUK#TRPBF
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LTC2123IUK
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →LTC2123CUK#PBF
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LTC2122CUK
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →LTC2123CUK Tỷ lệ tối đa & tính chất điện
| Độ phân giải | 14 bit |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate | 250 Msps |
| Architecture | Pipelined |
| Input Bandwidth | 1.25 GHz |
| SNR | 70 dBFS |
| SFDR | 90 dBFS |
| Digital Output Interface | JESD204B |
| Điện áp cung cấp | 1.8 V (single) |
| Hộp | 48-QFN (7x7 mm) |
| Kiểu lắp đặt | Surface Mount |
| Khoảng nhiệt độ hoạt động | 0 C to 70 C (commercial) |
| Lead-Free / RoHS | Yes (PBF suffix) |
| Số lượng chân | 48 |
| Input Type | Differential analog (per channel) |
Cấu hình chân LTC2123CUK
| Chân 1 | INA+ — Channel A positive differential analog input |
| Chân 2 | INA- — Channel A negative differential analog input |
| Chân 3 | VCM_A — Channel A common-mode voltage |
| Chân 4 | INB+ — Channel B positive differential analog input |
| Chân 5 | INB- — Channel B negative differential analog input |
| Chân 6 | VCM_B — Channel B common-mode voltage |
| Chân 7 | AVDD — 1.8 V analog supply |
| Chân 8 | AGND — Analog ground |
| Chân 9 | AVDD — 1.8 V analog supply |
| Chân 10 | AGND — Analog ground |
| Chân 11 | CKP — Sample clock positive input |
| Chân 12 | CKN — Sample clock negative input |
| Chân 13 | PLLVDD — PLL 1.8 V supply |
| Chân 14 | PLLGND — PLL ground |
| Chân 15 | DVDD — 1.8 V digital core supply |
| Chân 16 | DGND — Digital ground |
| Chân 17 | DRVDD — 1.8 V serial-output driver supply |
| Chân 18 | DRGND — Serial-output driver ground |
| Chân 19 | OUT0+ — JESD204B serial lane 0 positive |
| Chân 20 | OUT0- — JESD204B serial lane 0 negative |
| Chân 21 | OUT1+ — JESD204B serial lane 1 positive |
| Chân 22 | OUT1- — JESD204B serial lane 1 negative |
| Chân 23 | OUT2+ — JESD204B serial lane 2 positive |
| Chân 24 | OUT2- — JESD204B serial lane 2 negative |
| Chân 25 | OUT3+ — JESD204B serial lane 3 positive |
| Chân 26 | OUT3- — JESD204B serial lane 3 negative |
| Chân 27 | NC — Not connected (per datasheet) |
| Chân 28 | NC — Not connected (per datasheet) |
| Chân 29 | MODE — Operating mode select (LVDS/CMOS clock, lane count, etc.) |
| Chân 30 | CS — SPI chip select |
| Chân 31 | SCK — SPI serial clock |
| Chân 32 | SDI — SPI serial data in |
| Chân 33 | SDO — SPI serial data out |
| Chân 34 | RESET — Global reset (active low) |
| Chân 35 | PDWN — Global power-down (active low) |
| Chân 36 | NC — Not connected (per datasheet) |
| Chân 37 | NC — Not connected (per datasheet) |
| Chân 38 | SYNCAB — JESD204B synchronization request for both A and B channels |
| Chân 39 | NC — Not connected (per datasheet) |
| Chân 40 | NC — Not connected (per datasheet) |
| Chân 41 | DRVDD — 1.8 V serial-output driver supply |
| Chân 42 | DRGND — Serial-output driver ground |
| Chân 43 | DVDD — 1.8 V digital core supply |
| Chân 44 | DGND — Digital ground |
| Chân 45 | AVDD — 1.8 V analog supply |
| Chân 46 | AGND — Analog ground |
| Chân 47 | AVDD — 1.8 V analog supply |
| Chân 48 | AGND — Analog ground |
Ứng dụng tiêu biểu
LTC2123CUK phù hợp cho 6 Áp dụngs: Multi-Antenna Diversity Receivers, IF Digitizers for Wireless Base Stations, Broadband Test & Measurement Instrumentation, Phased-Array Radar Signal Chains, High-Speed Data Acquisition Test Systems, Software Defined Radio (SDR) Wideband Receivers.
Multi-Antenna Diversity Receivers
In diversity receivers for 4G/5G base stations, simultaneous sampling of two antenna streams requires analog-to-digital converters that preserve phase alignment. The LTC2123CUK's dual-channel simultaneous-sampling architecture with 250 Msps and 70 dBFS SNR captures two independent RF outputs without inter-channel skew; 1.25 GHz input bandwidth handles multi-band IFs cleanly. The JESD204B Subclass 1 deterministic latency output keeps the two channels frame-aligned into a single FPGA SERDES, eliminating parallel CMOS data buses and 50+ PCB traces. Designers benefit from lower FPGA pin count and lower BOM, with about 90 dBFS SFDR maintaining EVM budget for high-order modulations.
Được đề xuất
IF Digitizers for Wireless Base Stations
In 3G/4G/5G base-station receivers, the LTC2123CUK samples IF signals in the second or third Nyquist zone thanks to its 1.25 GHz input bandwidth, eliminating one analog downconversion stage. Operating at 250 Msps from a single 1.8 V rail, the converter achieves 70 dBFS SNR and 90 dBFS SFDR - tight enough for 64-QAM and 256-QAM with low EVM penalty. The JESD204B interface supports up to 4 serial lanes and Subclass 1 deterministic latency, letting the radio baseband ASIC recover phase-aligned I/Q streams without large FIFOs between the converter and DSP fabric.
Được đề xuất
Broadband Test & Measurement Instrumentation
High-bandwidth oscilloscopes, spectrum analyzers, and signal analyzers need fast ADC front ends to capture wideband transient or modulated signals. The LTC2123CUK's 250 Msps real-time sampling rate delivers 125 MHz Nyquist analog bandwidth, and its 70 dBFS SNR supports greater than 11-bit effective resolution for fine-grained spectral measurements. Dual channels enable simultaneous stimulus/response or two-channel acquisition paths; the JESD204B serial output allows instrumentation firmware to keep the analog front end electrically isolated from the host FPGA processing card.
Được đề xuất
Phased-Array Radar Signal Chains
Phased-array radar subsystems use multiple synchronized analog-to-digital converters, one per antenna element, to capture coherent phase across the array. The LTC2123CUK's dual-channel simultaneous sampling at 250 Msps pairs neatly into adjacent receive channels, cutting the converter count roughly in half versus single-channel parts. 70 dBFS SNR plus 90 dBFS SFDR preserve dynamic range across the array, while JESD204B Subclass 1 deterministic latency ensures time-of-arrival consistency at the radar DSP. The 48-QFN thermally optimized package suits array PCBs where board-to-board spacing is tight.
Được đề xuất
High-Speed Data Acquisition Test Systems
Lab-grade data-acquisition systems, telemetry recorders, and protocol analyzers use high-sample-rate analog-to-digital converters to digitize wideband analog signals at full fidelity for offline analysis. With the LTC2123CUK, a 250 Msps sample rate captures up to 125 MHz of analog bandwidth in a single Nyquist window, while 90 dBFS SFDR ensures harmonics and spurs stay invisible in the captured waveform. Dual channels enable simultaneous multi-node measurements; the JESD204B output streams captured data straight into an FPGA processing board without the routing density of parallel LVDS interfaces, easing mechanical stack-up for compact bench instruments.
Được đề xuất
Software Defined Radio (SDR) Wideband Receivers
In software-defined radio baseband receivers, moving the analog-to-digital boundary closer to the antenna improves flexibility and reduces analog tunables. The LTC2123CUK samples broadband IF up to 1.25 GHz at 250 Msps, giving software-defined systems direct access to filtered slices of the spectrum without hardware retuning. The 14-bit resolution at 70 dBFS SNR supports demodulation of high-order constellations, while JESD204B output connects cleanly to radio-DSP FPGAs and ASICs. Two independent simultaneous channels are well suited to dual-channel I/Q or diversity reception in a single receiver card.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho LTC2123CUK — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | LTC2123CUK#TRPBF | LTC2123IUK | LTC2123CUK#PBF | LTC2122CUK |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 48-QFN (7x7) | 48-QFN (7x7) - same | 48-QFN (7x7) - same | 48-QFN (7x7) - same | 48-QFN (7x7) - same |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit |
| Sample Rate | 250 Msps | 250 Msps | 250 Msps | 250 Msps | 170 Msps |
| Channels | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) |
| Temperature Range | 0 C to 70 C (commercial) | 0 C to 70 C (commercial) | -40 C to +85 C (industrial) | 0 C to 70 C (commercial) | 0 C to 70 C (commercial) |
| Output Interface | JESD204B | JESD204B | JESD204B | JESD204B | JESD204B |
| Lead-Free / RoHS | Yes (PBF suffix) | Yes | Yes | Yes | Yes |
Bảo phân biệt quan trọng
- Industrial temperature grade available on identical footprint (vsLTC2123IUK)
- Sample rate advantage over LTC2122 family (vsLTC2122CUK)
- Lead-free (PBF) version on identical die (vsLTC2123CUK#PBF)
Ghi chú thiết kế
The 48-QFN exposed thermal pad on the LTC2123CUK MUST be soldered to a continuous ground island - thermal vias stitched into this pad keep the die junction within the 0 to 70 C commercial range at full 250 Msps operation. Use 50 ohm controlled-impedance routing for the differential analog input pairs (INA+/INA-, INB+/INB-) and the CKP/CKN clock pair; keep trace lengths matched to within 0.1 inch to avoid ISL jitter penalty at sample instant.
Estimated: the LTC2123CUK draws roughly [DATA_NEEDED] from AVDD plus a similar amount from DVDD/DRVDD at full 250 Msps. Place 0.1 uF X7R ceramics as close as practical to each AVDD and DVDD pin and use a ferrite bead to isolate any switching noise from the rail source. Keep analog and digital return currents physically separated until they reach the device exposed pad to prevent substrate bounce from polluting the analog input network.
Do not assume that JESD204B configuration is automatic - the LTC2123CUK requires explicit SPI programming of the SERDES PLL, lane assignment, and Subclass 1 deterministic latency before link bring-up can occur. Use a long enough initial alignment character (ILAS) sequence as recommended by the family datasheet, and verify receive-ready (SYNCAB) is de-asserted only after the FPGA receiver detects K28.5 characters; otherwise the converter will not begin emitting sample data.
Thông tin tuân thủ
LTC2123CUK#PBF suffix confirms lead-free and RoHS-compliant per the Analog Devices ordering information. Industrial variant LTC2123IUK shares the same RoHS status. No AEC-Q100 qualification for this family.