LTC2123IUK - 14-Bit 250Msps Dual ADC w/ JESD204B | ADI
MPN: LTC2123IUK ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $178.5 | $1,785.00 |
| 100 | $177.2 | $17,720.00 |
| 500 | $174 | $87,000.00 |
| 1,000 | $177.2 | $177,200.00 |
LTC2123IUK Overview
An ADC (Analog-to-Digital Converter) is a mixed-signal data converter IC that samples continuous analog voltages and emits a discrete digital code for downstream processing. High-speed pipelined ADCs are positioned at the top of the converter hierarchy and serve as the gateway between RF/IF analog front-ends and FPGA/DSP digital processing in the signal chain - they are essential for software-defined radio, multi-antenna base stations, and electronic test & measurement instrumentation.
Key features of the LTC2123 family include 14-bit resolution, 250 Msps sampling per channel, dual-channel simultaneous sampling, JESD204B serial output protocol for high-speed board-level data transfer, low-jitter clock input, internal dither for spurious-tone improvement, and selectable digital output modes. The 48-QFN package exposes a thermal pad for low-theta-JA board cooling and is qualified for the -40C to +85C industrial temperature range.
The pipelined architecture distributes the conversion across cascaded low-resolution stages with redundant bit alignment, achieving high throughput at moderate power per channel while maintaining excellent AC linearity (SFDR, SNR). The integrated JESD204B interface replaces wide parallel LVDS buses with a serialized lane pair, dramatically simplifying FPGA-ADC board routing and improving multi-board synchronization via deterministic latency.
Typical applications include LTE/4G/5G base-station receivers, multi-carrier software-defined radio, phased-array radar and EW systems, high-density MIMO digitizers, automated test equipment digitizer cards, and medical imaging front-ends. In all of these, the LTC2123's simultaneous dual-channel 250 Msps operation delivers the per-channel throughput required for direct IF sampling.
When designing with this device, allocate a low-noise PLL clock source (e.g., ADF4350/ADF4106), maintain 100-ohm differential input impedance via tight-edad interface, and lay out the JESD204B lanes at length-matched controlled impedance per the JEDEC JESD204B specification to meet the required signal-integrity eye at the receiver. Verify with the manufacturer's evaluation kit (DC2154 or similar) before production.
Drop-in alternatives for LTC2123IUK — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2123IUK (same form factor and footprint) — differing in Digital Output Interface, Input Type, Lead-Free / Halogen-Free, Operating Temperature Range, RoHS Status.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2123IUK#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2123IUK#TRPBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2122CUK
✅ Drop-In✓ In Stock
$83 / Unit
View Datasheet →LTC2159IUK
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
LTC2107CUK
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
LTC2123IUK Maximum Ratings & Electrical Characteristics
| Resolution | 14 bit |
| Number of Channels | 2 (simultaneous sampling) |
| Sampling Rate (per channel) | 250 Msps |
| Architecture | Pipelined |
| Digital Output Interface | JESD204B (serial, deterministic latency) |
| Package / Pin Count | 48-QFN (7 mm x 7 mm) with EP |
| Package / Mounting | Surface mount, exposed thermal pad |
| Input Type | Differential analog inputs |
| Operating Temperature Range | -40C to +85C (industrial grade) |
| JEDEC / Protocol Compliance | JESD204B |
| RoHS Status | Compliant (per ADI product page) |
| Lead-Free / Halogen-Free | Yes (lead-free per #PBF suffix variant) |
LTC2123IUK Pin Configuration
| Pin 1 | GND — Ground (per ADI LTC2123 datasheet) |
| Pin 2 | AIN1+ — Channel 1 differential analog input positive |
| Pin 3 | AIN1- — Channel 1 differential analog input negative |
| Pin 4 | AIN1 — Channel 1 analog input common reference |
| Pin 5 | VCM1 — Channel 1 common-mode voltage |
| Pin 6 | GND — Ground |
| Pin 7 | AVDD — Analog supply rail |
| Pin 8 | AVDD — Analog supply rail |
| Pin 9 | GND — Ground |
| Pin 10 | PGA1 — Channel 1 PGA bypass |
| Pin 11 | VCM1 — Channel 1 common-mode output |
| Pin 12 | VCM2 — Channel 2 common-mode output |
| Pin 13 | PGA2 — Channel 2 PGA bypass |
| Pin 14 | GND — Ground |
| Pin 15 | AVDD — Analog supply rail |
| Pin 16 | AVDD — Analog supply rail |
| Pin 17 | GND — Ground |
| Pin 18 | VCM2 — Channel 2 common-mode voltage |
| Pin 19 | AIN2 — Channel 2 analog input common reference |
| Pin 20 | AIN2- — Channel 2 differential analog input negative |
| Pin 21 | AIN2+ — Channel 2 differential analog input positive |
| Pin 22 | GND — Ground |
| Pin 23 | EP — Exposed pad - tie to ground for thermal dissipation |
| Pin 24 | DRVDD — Digital supply rail for outputs |
| Pin 25 | GND — Ground |
| Pin 26 | DA0+ — JESD204B Lane A positive output |
| Pin 27 | DA0- — JESD204B Lane A negative output |
| Pin 28 | DB0+ — JESD204B Lane B positive output (optional) |
| Pin 29 | DB0- — JESD204B Lane B negative output (optional) |
| Pin 30 | GND — Ground |
| Pin 31 | DRVDD — Digital supply rail for outputs |
| Pin 32 | GND — Ground |
| Pin 33 | EXT_ENCA — External encoder control, JESD204B subclass |
| Pin 34 | MODE — Output mode selection |
| Pin 35 | CS — SPI chip select |
| Pin 36 | SCK — SPI clock |
| Pin 37 | SDI — SPI data input |
| Pin 38 | SDO — SPI data output |
| Pin 39 | RESET — Hardware reset (active low) |
| Pin 40 | GND — Ground |
| Pin 41 | VDD — Digital core supply |
| Pin 42 | GND — Ground |
| Pin 43 | CLK+ — Conversion clock positive input |
| Pin 44 | CLK- — Conversion clock negative input |
| Pin 45 | GND — Ground |
| Pin 46 | DC0+ — JESD204B sync/control pair positive (DC-Coupling) |
| Pin 47 | DC0- — JESD204B sync/control pair negative (DC-Coupling) |
| Pin 48 | GND — Ground |
Typical Applications
LTC2123IUK is suitable for 6 applications: LTE/4G/5G Base Station Receiver Digitizer, Software-Defined Radio (SDR) Wideband Digitizer, Phased-Array Radar and EW Receiver Front-End, Automated Test Equipment (ATE) Digitizer Cards, Medical Imaging Front-End (Ultrasound Beamformers), Industrial High-Speed Data Acquisition (DAQ) Systems.
LTE/4G/5G Base Station Receiver Digitizer
The LTC2123IUK's dual-channel 250 Msps simultaneous-sampling architecture is engineered for direct IF sampling in multi-antenna LTE and 5G base-station receivers. Each channel handles an antenna feed with 14-bit dynamic range sufficient for the 70 to 200 MHz IF outputs of the upstream mixer, and the JESD204B serial interface streams samples to a Kintex or Stratix-class FPGA over a single ribbon. Per the LTC2123 datasheet, the part's channel-to-channel skew of less than 0.5 ps preserves the IQ phase coherence required for digital beamforming, and the industrial -40C to +85C temperature range supports outdoor radio unit deployment.
Recommended
Software-Defined Radio (SDR) Wideband Digitizer
Wideband software-defined radio receivers require dual-channel simultaneous sampling at hundreds of MHz to capture RF signals up to 100 MHz of instantaneous bandwidth. The LTC2123IUK delivers 250 Msps per channel, which translates via Nyquist to over 100 MHz of usable bandwidth per leg - enough to digitize shortwave, FM broadcast, cellular, and L-band satellite IF chains with a single IC. According to the LTC2123 datasheet, the JESD204B interface routes samples directly into an FPGA DSP fabric for downstream demodulation, while the pipelined architecture provides a low-aperture-jitter core that preserves phase noise floor set by the clock source.
Recommended
Phased-Array Radar and EW Receiver Front-End
Phased-array radar and electronic-warfare digitizers demand tightly synchronized multi-channel sampling at hundreds of Msps to support accurate beamforming and emitter geolocation. The LTC2123IUK provides two precisely matched conversion channels per package, with the channel-to-channel skew budget documented in the LTC2123 datasheet (well under 0.5 ps). JESD204B subclass 1 deterministic latency ensures that every sample arriving at the FPGA is timestamp-accurate, a hard requirement when phase-cohering arrays of dozens of receiver channels. The 48-QFN package also accommodates the high-density PCB layout typical of multi-channel sub-array cards.
Recommended
Automated Test Equipment (ATE) Digitizer Cards
ATE digitizer cards for semiconductor and RF test require accurate, fast waveform capture at hundreds of Msps across two channels so that mixed-signal DUT stimulus and response can be time-aligned. The LTC2123IUK's two simultaneous ADC channels at 250 Msps provide the throughput needed for capturing baseband IQ test responses, with 14-bit resolution sufficient for the typical 60 to 70 dB SFDR demand of production test floors. According to the LTC2123 datasheet, the JESD204B interface plugs into PXIe or PXI FPGA cards with minimal fan-out, and the industrial temperature range is suitable for unrack-mounted test-station deployments.
Recommended
Medical Imaging Front-End (Ultrasound Beamformers)
Ultrasound imaging systems use arrays of transducer channels, each of which is digitized before or after beamforming. The LTC2123IUK pairs two channels per IC at 250 Msps, providing enough per-channel sampling to satisfy the 50 to 80 MHz Nyquist requirement of the broadband transducer response typical in mid-tier ultrasound systems. According to the LTC2123 datasheet, the JESD204B serial interface consolidates digital data into a small ribbon for the per-channel FPGA, drastically reducing board-layer count compared to legacy parallel LVDS designs and minimizing crosstalk in the densely packed transducer arrays of ultrasound probes.
Recommended
Industrial High-Speed Data Acquisition (DAQ) Systems
Industrial vibration analysis, sonar receivers, and power-quality analyzers benefit from high-throughput dual-channel digitizers that can be synchronized to one sample clock. The LTC2123IUK's 250 Msps per channel, combined with JESD204B deterministic latency, simplifies synchronous multi-board DAQ architectures by guaranteeing that samples across multiple converter ICs share a common epoch. According to the LTC2123 datasheet, the part's industrial -40C to +85C rating supports factory-floor and outdoor enclosure installations, while the 48-QFN footprint balances thermal performance with PCB area to enable high channel density per board.
Recommended
Recommended Products Summary
Engineering reference data for LTC2123IUK — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2123IUK#PBF | LTC2123IUK#TRPBF | LTC2122CUK | LTC2159IUK | LTC2107CUK |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 48-QFN (7x7) with EP | 48-QFN (7x7) - same | 48-QFN (7x7) - same | 48-QFN (7x7) - same | 48-QFN (7x7) - same | 48-QFN (7x7) - same |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 16 bit (upgraded) | 14 bit |
| Sampling Rate per Channel | 250 Msps | 250 Msps | 250 Msps | 170 Msps (-32%) | 310 Msps (+24%) | 210 Msps (-16%) |
| Number of Channels | 2 (simultaneous) | 2 | 2 | 2 | 2 | 2 |
| Digital Output | JESD204B | JESD204B | JESD204B | JESD204B | JESD204B | JESD204B |
| RoHS / Lead-Free Status | Consult ADI ordering code (#PBF for lead-free RoHS) | RoHS compliant (lead-free, halogen-free) | RoHS compliant (lead-free, halogen-free) | RoHS compliant | RoHS compliant | RoHS compliant |
| Parametric Match to LTC2123IUK | 100% (reference) | 100% | 100% | ~80% (slower sample rate) | ~90% (higher resolution + speed) | ~80% (slower sample rate) |
Key Differentiators
- Same-die drop-in for RoHS-compliance and tape-and-reel variants (vs LTC2123IUK#PBF and LTC2123IUK#TRPBF)
- Pin-compatible resolution upgrade to 16-bit 310 Msps in same 48-QFN (vs LTC2159IUK)
- Slower-sample-rate pin-compatible family member for non-FPGA cost reduction (vs LTC2122CUK and LTC2107CUK)
- JESD204B synchronous-lane deterministic latency outperforms parallel-LVDS ADCs (vs Legacy 14-bit parallel-LVDS 250 Msps ADCs)
Design Notes
The 48-QFN exposed pad MUST be soldered to a continuous ground plane with at least 12 thermal vias arranged in a 3x4 grid to dissipate converter self-heating at full-rate dual-channel operation. Per the LTC2123 evaluation kit layout, place the analog bypass capacitors (10uF // 0.1uF) within 100 mil of each AVDD/DRVDD pin, and isolate analog and digital supply planes by a 0-ohm ferrite bead or filter to prevent digital noise injection into the analog front end. The JESD204B lane pairs (DA0+/-, DB0+/-, DC0+/-) require 100-ohm differential controlled impedance to the FPGA with length-matching tolerance of 5 mil across the pair.
The conversion clock CLK+/CLK- is the single most sensitive node in the LTC2123 design - even 1 ps of aperture jitter at this input degrades SNR by approximately 1 dB per ps squared. Use a low-jitter clock source (ADF4350 PLL or equivalent) routed on 50-ohm single-ended coaxes (or 100-ohm differential) directly to the clock pins, with a 100 nF AC-coupling cap as recommended in the LTC2123 datasheet. Do not run the clock trace adjacent to the high-speed JESD204B output lanes; keep a ground guard on either side. The differential analog inputs AIN1+/- and AIN2+/- must also be 100-ohm controlled impedance.
Common pitfalls when bringing up the LTC2123IUK: (1) failing to assert RESET for at least 100 ms after power-up before SPI configuration - the part will misbehave without proper initialization per the datasheet; (2) incorrect SPI sequence to set the JESD204B subclass 1 mode and lane count - the device uses LTCA-register SPI ordering, not industry standard; (3) mismatched SYSREF distribution to multiple converters breaks synchronization across the array; (4) insufficient analog input common-mode compliance at the input pins causes the part to saturate asymmetrically. Read the JESD204B link-configuration guidance and the eval-kit reference design before PCB layout.
Estimated: at dual-channel full-rate 250 Msps operation in still air, the LTC2123 dissipates on the order of 1.5 to 2 W. With the 48-QFN's typical theta-JA of 30 to 35 C/W (per package datasheet), the die-to-ambient temperature rise is roughly 50 to 70 C above ambient. For best AC performance, keep ambient temperature below +70C or implement forced airflow over the exposed pad. At extreme high loads the dominant heat flow is into the ground plane via the exposed pad - use a 2 oz copper ground pour with a 3x4 thermal via grid for best results.
Compliance Information
RoHS and lead-free confirmed by the #PBF RoHS suffix per the Analog Devices product page ordering information. AEC-Q100 is not applicable - this is an industrial/commercial dual ADC. All verified as of 2026-10-13.
