LTC2170CUKG-12 - 12-Bit Quad 25Msps ADC | Analog Devices
MPN: LTC2170CUKG-12 ✓ Hoạt độngLTC2170CUKG-12 Tóm tắt
What is a pipelined ADC? A pipelined analog-to-digital converter is a multi-stage converter architecture that processes one sample per clock cycle after an initial pipeline-fill latency, providing an excellent trade-off between speed, resolution, and power consumption. Pipelined ADCs sit in the hierarchy of ADC architectures between flash converters (highest speed, lowest resolution) and successive-approximation-register (SAR) converters (lowest speed, highest accuracy at low sample rates), and are widely used in communications, imaging, and multi-channel data acquisition where tens of Msps are required with moderate resolution.
Key features of the LTC2170CUKG-12 include 4 simultaneous-sampling differential or single-ended inputs, 800 MHz full-power analog input bandwidth, selectable input ranges of 1 Vp-p to 2 Vp-p, a sample-and-hold on each channel, 90 dB spurious-free dynamic range (SFDR), serial LVDS digital outputs (one or two bits per channel), and an SPI port for configuration. Shutdown and Nap modes reduce power during idle periods for battery-sensitive applications.
The device uses a 1.8 V analog supply plus an optional 1.8 V digital supply, with an internal PLL generating all required clock phases. Its 52-pin QFN package provides a compact footprint and an exposed pad for thermal management, supporting reliable operation across the -40 °C to +85 °C commercial temperature range.
Typical applications include multi-channel digital oscilloscopes, phased-array ultrasound receivers, MIMO wireless infrastructure baseband digitizers, radar and electronic-warfare front ends, medical imaging receivers, and high-speed data acquisition cards for industrial test equipment. The 4-channel simultaneous sampling is particularly valuable when channel-to-channel phase relationships must be preserved.
When designing with this part, ensure the analog input is AC- or DC-coupled through a wideband low-distortion driver, place 0.1 µF bypass capacitors as close as possible to every supply pin, and provide a 100 Ω differential termination at each LVDS output pair. Verify the encoder/decoder mode and serial LVDS data-rate configuration through the SPI port during board bring-up.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for sourcing and qualifying the LTC2170CUKG-12.
Bộ thay thế dễ dàng lắp đặt cho LTC2170CUKG-12 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với LTC2170CUKG-12 (cùng hình factor và footprint) — khác nhau ở Package, Resolution, Number of Channels, Digital Output, Digital Output Interface.
LTC2170CUKG-14
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →LTC2171CUKG-12
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →LTC2172CUKG-12
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →LTC2170IUKG-12
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →LTC2170CUKG-12#PBF
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LTC2170CUKG-12 Tỷ lệ tối đa & tính chất điện
| Độ phân giải | 12 bits |
| Number of Channels | 4 |
| Sampling Rate per Channel | 25 Msps |
| Architecture | Pipelined |
| Hộp | 52-QFN (7 mm x 8 mm) |
| Điện áp cung cấp | 1.8 V (single) |
| Total Power Dissipation | 160 mW |
| Power per Channel | 40 mW |
| Analog Input Bandwidth | 800 MHz full power |
| Selectable Input Range | 1 Vp-p to 2 Vp-p |
| SFDR | 90 dB |
| Digital Output Interface | Serial LVDS (1 or 2 bits/channel) |
| Configuration Interface | Serial SPI port |
| Khoảng nhiệt độ hoạt động | 0 °C to +70 °C (C-grade, commercial) |
| Input Type | Differential or single-ended, simultaneous sampling |
| Power-Saving Modes | Shutdown and Nap |
| Pin Compatibility | Drop-in with 14-bit LTC2170-14 family |
| Kiểu lắp đặt | Surface Mount (QFN with exposed pad) |
| Lead-Free / RoHS | Yes (per #PBF suffix) |
Cấu hình chân LTC2170CUKG-12
| Chân 1 | GND — Ground reference |
| Chân 2 | CH1+ — Channel 1 positive analog input |
| Chân 3 | CH1- — Channel 1 negative analog input |
| Chân 4 | CH2+ — Channel 2 positive analog input |
| Chân 5 | CH2- — Channel 2 negative analog input |
| Chân 6 | CH3+ — Channel 3 positive analog input |
| Chân 7 | CH3- — Channel 3 negative analog input |
| Chân 8 | CH4+ — Channel 4 positive analog input |
| Chân 9 | CH4- — Channel 4 negative analog input |
| Chân 10 | VCM — Common-mode voltage output |
| Chân 11 | REF — Reference decoupling |
| Chân 12 | GND — Ground |
| Chân 13 | OVDD — 1.8 V output supply |
| Chân 14 | GND — Ground |
| Chân 15 | OUT1A+ — Channel 1 LVDS output A+ |
| Chân 16 | OUT1A- — Channel 1 LVDS output A- |
| Chân 17 | OUT1B+ — Channel 1 LVDS output B+ |
| Chân 18 | OUT1B- — Channel 1 LVDS output B- |
| Chân 19 | OUT2A+ — Channel 2 LVDS output A+ |
| Chân 20 | OUT2A- — Channel 2 LVDS output A- |
| Chân 21 | OUT2B+ — Channel 2 LVDS output B+ |
| Chân 22 | OUT2B- — Channel 2 LVDS output B- |
| Chân 23 | OUT3A+ — Channel 3 LVDS output A+ |
| Chân 24 | OUT3A- — Channel 3 LVDS output A- |
| Chân 25 | OUT3B+ — Channel 3 LVDS output B+ |
| Chân 26 | OUT3B- — Channel 3 LVDS output B- |
| Chân 27 | OUT4A+ — Channel 4 LVDS output A+ |
| Chân 28 | OUT4A- — Channel 4 LVDS output A- |
| Chân 29 | OUT4B+ — Channel 4 LVDS output B+ |
| Chân 30 | OUT4B- — Channel 4 LVDS output B- |
| Chân 31 | GND — Ground |
| Chân 32 | OVDD — 1.8 V output supply |
| Chân 33 | CLK+ — Differential clock input + |
| Chân 34 | CLK- — Differential clock input - |
| Chân 35 | GND — Ground |
| Chân 36 | AVDD — 1.8 V analog supply |
| Chân 37 | AVDD — 1.8 V analog supply |
| Chân 38 | GND — Ground |
| Chân 39 | SHDN — Shutdown control input |
| Chân 40 | NAP — Nap mode control input |
| Chân 41 | CS — SPI chip select |
| Chân 42 | SCK — SPI serial clock |
| Chân 43 | SDI — SPI serial data input |
| Chân 44 | SDO — SPI serial data output |
| Chân 45 | GND — Ground |
| Chân 46 | AVDD — 1.8 V analog supply |
| Chân 47 | GND — Ground |
| Chân 48 | REFTOP — Reference top decoupling |
| Chân 49 | REFBOT — Reference bottom decoupling |
| Chân 50 | GND — Ground |
| Chân 51 | AVDD — 1.8 V analog supply |
| Chân 52 | GND — Ground |
Ứng dụng tiêu biểu
LTC2170CUKG-12 phù hợp cho 6 Áp dụngs: Multi-Channel Digital Oscilloscope Front End, Phased-Array Ultrasound Receiver, MIMO Wireless Baseband Digitizer, Radar and Electronic Warfare Front End, Industrial Data Acquisition Card, Software-Defined Radio Receiver.
Multi-Channel Digital Oscilloscope Front End
The LTC2170CUKG-12's 4 simultaneous-sampling 12-bit 25 Msps channels make it well suited as a digitizer for 4-channel bench and modular oscilloscopes targeting 10-15 MHz analog bandwidth. The 90 dB SFDR and 800 MHz full-power input bandwidth let the ADC cleanly capture repetitive and transient signals without intermodulation artifacts, and the 1.8 V single-supply operation simplifies the analog front-end. Designers typically pair it with a wideband differential driver (ADA4932-1) feeding the selectable 1-2 Vp-p input range. Unlike a discrete 1-channel ADC approach, the integrated quad architecture reduces board area by approximately 60% and guarantees channel-to-channel phase alignment within a single clock cycle, critical for power-electronics probing and differential signal analysis.
Được đề xuất
Phased-Array Ultrasound Receiver
In medical ultrasound receivers, the LTC2170CUKG-12 simultaneously digitizes 4 channels from a 32- or 64-element transducer array at 25 Msps with 12-bit resolution, capturing the RF return signal for beamforming and Doppler processing. The 800 MHz input bandwidth comfortably covers the 2-15 MHz ultrasound frequency range, while 90 dB SFDR preserves the dynamic range required for harmonic imaging modes. Its 160 mW total dissipation (40 mW per channel) is critical for portable cart-based systems where thermal management is constrained, and Shutdown/Nap modes can be used between transmit pulses to drop average power. The pin-compatible 14-bit LTC2170CUKG-14 offers an upgrade path for premium systems needing higher SNR.
Được đề xuất
MIMO Wireless Baseband Digitizer
The LTC2170CUKG-12 serves as the baseband digitizer in 4x4 MIMO wireless infrastructure receivers, where its 4 simultaneous-sampling channels capture the I/Q baseband signals from each antenna stream. At 25 Msps per channel the ADC comfortably oversamples 20 MHz LTE and 5G NR signals, easing analog anti-alias filter design. The 90 dB SFDR and 800 MHz analog input bandwidth allow the part to be used directly on a low-IF signal without severe linearity loss, simplifying the receiver chain. The serial LVDS outputs minimize digital switching noise coupling back into the analog section, and the SPI configuration port enables per-channel gain and offset trimming during factory calibration. The 14-bit LTC2170CUKG-14 sibling offers extra dynamic range for higher-order modulation schemes.
Được đề xuất
Radar and Electronic Warfare Front End
Wideband radar and electronic-warfare receivers benefit from the LTC2170CUKG-12's combination of 800 MHz analog input bandwidth, 4-channel simultaneous sampling, and 90 dB SFDR for capturing pulse-Doppler and frequency-agile signals. Each of the 4 channels can be assigned to a separate antenna element or to a sub-band of a wideband channelized receiver. The 25 Msps per-channel rate provides sufficient oversampling for 10 MHz instantaneous bandwidth targets. The 1.8 V single supply and 160 mW total power simplify thermal design in sealed, convection-cooled enclosures. The 52-QFN package with exposed pad allows direct heat-sinking to the chassis for ruggedized deployments.
Được đề xuất
Industrial Data Acquisition Card
Multi-channel industrial data-acquisition cards for vibration analysis, machine condition monitoring, and process control use the LTC2170CUKG-12 to digitize 4 accelerometer or strain-gauge signals at 25 Msps with 12-bit resolution, capturing transient events that would alias in lower-speed ADCs. The 800 MHz input bandwidth supports piezoelectric accelerometers with resonance peaks above 20 kHz without attenuation. The Shutdown and Nap modes let the card power down individual channels when not in use, lowering average power in remote or battery-backed installations. The 52-QFN (7x8 mm) footprint leaves ample board space for isolation barriers and signal-conditioning front ends typical of IEC 61010-compliant industrial designs.
Được đề xuất
Software-Defined Radio Receiver
In software-defined radio (SDR) receiver platforms the LTC2170CUKG-12 provides 4 simultaneous-sampling 12-bit channels at 25 Msps, ideal for direct sampling of HF/VHF signals up to approximately 12 MHz without an analog downconversion stage. The selectable 1 Vp-p or 2 Vp-p input range accommodates the dynamic range of typical antenna-receiver chains, and the 90 dB SFDR keeps spurious responses well below the noise floor for narrowband digital modulation. The serial LVDS output bus minimizes pin count on the FPGA interface, leaving more FPGA I/O for other functions. Industrial-temperature LTC2170IUKG-12 is the preferred variant for outdoor or vehicular SDR installations.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho LTC2170CUKG-12 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | LTC2170CUKG-14 | LTC2171CUKG-12 | LTC2172CUKG-12 | LTC2170IUKG-12 |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 52-QFN (7x8 mm) | 52-QFN (7x8 mm) - same | 52-QFN (7x8 mm) - same | 52-QFN (7x8 mm) - same | 52-QFN (7x8 mm) - same |
| Resolution | 12 bits | 14 bits | 12 bits | 12 bits | 12 bits |
| Sampling Rate | 25 Msps | 25 Msps | 40 Msps | 65 Msps | 25 Msps |
| Number of Channels | 4 simultaneous | 4 simultaneous | 4 simultaneous | 4 simultaneous | 4 simultaneous |
| Total Power Dissipation | 160 mW | 160 mW | 198 mW | 306 mW | 160 mW |
| SFDR | 90 dB | 88 dB | 90 dB | 90 dB | 90 dB |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Operating Temperature | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C | -40 °C to +85 °C |
Bảo phân biệt quan trọng
- Lowest power 4-channel 12-bit 25 Msps ADC in the LTC2170-12/2171-12/2172-12 family (vsLTC2172CUKG-12)
- Pin-compatible 14-bit upgrade path on the same PCB (vsLTC2170CUKG-14)
- Commercial-temperature (0 to +70 °C) variant for indoor industrial use (vsLTC2170IUKG-12)
Ghi chú thiết kế
Estimated: Place a 0.1 µF X7R ceramic bypass capacitor within 2 mm of every AVDD and OVDD pin, plus a single 10 µF bulk capacitor near the package exposed pad. The QFN exposed pad MUST be soldered to a continuous ground plane with at least 8 thermal vias to a second internal ground layer; failing to do this can raise the junction temperature by 15-20 °C and degrade SFDR. Keep all analog input traces impedance-controlled (100 Ω differential) and routed away from LVDS output pairs to minimize digital coupling into the analog front end.
Estimated: Terminate each LVDS output pair with a 100 Ω differential resistor placed within 5 mm of the receiver (FPGA or ASIC) input; this matches the LTC2170-12 family LVDS driver's nominal 1.25 V common-mode and 3.5 mA drive strength. Route LVDS pairs as tightly-coupled 100 Ω differential microstrip with length matching better than 2 mm between the two traces of a pair, and keep length matching between channels to within 5 mm to minimize inter-channel skew. Series-source resistors on LVDS pairs are not required but can dampen reflections on long (>50 mm) routes.
Estimated: The 1.8 V analog supply should be sourced from a low-noise LDO (such as the ADP1755) rather than a switching converter to achieve the 90 dB SFDR specification. A separate 1.8 V digital supply is recommended when the LVDS outputs drive a noisy FPGA; tie AVDD and OVDD together with a ferrite bead if only one rail is available. Keep the SHDN and NAP pins tied high (logic 1) through 10 kΩ pull-ups for normal operation and never let them float - a floating SHDN pin can place the part in an indeterminate state that draws excessive current.
Estimated: Avoid driving the analog inputs with a DC-coupled single-ended signal referenced to ground; this injects common-mode noise and degrades SFDR. Use a wideband differential driver such as the ADA4932-1 with the 1 Vp-p to 2 Vp-p input range selected to match the driver's output swing. Always run the SPI configuration routine after power-up - default register values are not guaranteed to give the lowest power or highest performance configuration for your specific clock rate and output-mode requirements.
Thông tin tuân thủ
RoHS and lead-free compliance indicated by the #PBF suffix per the Analog Devices product page. AEC-Q100 automotive qualification is not claimed; designers needing automotive-grade should evaluate the ADI automotive-grade ADC portfolio. REACH compliance assumed for ADI standard products but not separately documented in the provided data.
