LTC2172IUKG-12 - 12-Bit 65Msps Quad ADC, 52-QFN | Analog Devices
MPN: LTC2172IUKG-12 ⚠ Lần mua cuốiLTC2172IUKG-12 Tóm tắt
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes. The pipelined ADC architecture used in the LTC2172-12 family combines multiple low-resolution flash stages to achieve high sampling rates with low power consumption. The simultaneous-sampling quad-channel configuration is essential in applications where phase and amplitude relationships between channels must be preserved, such as in multi-antenna receivers, phased-array beamformers, and multi-channel test instrumentation.
Key features of the LTC2172IUKG-12 include 800 MHz full-power input bandwidth, individual channel shutdown and nap modes for power savings, a serial SPI port for configuration, and pin-compatibility with the 14-bit version. The device accepts differential inputs and outputs data in LVDS or CMOS formats, supporting flexible interface integration with FPGAs and DSPs. Typical SNR of approximately 70 dBFS at 65 Msps makes it suitable for communication infrastructure and industrial imaging systems.
Typical applications include communications receivers, cellular base-station digitizers, multi-channel data acquisition systems, medical imaging front ends, and portable or battery-powered instrumentation. The simultaneous-sampling nature preserves time-domain coherence across all four channels, which is critical for phased-array radar, ultrasound beamforming, and MIMO wireless front ends where mismatched sampling times would corrupt beam-steering calculations.
When designing with this part, place the analog input traces in a symmetric layout and route LVDS output pairs with controlled 100 ohm differential impedance. Use solid ground planes under the QFN thermal pad and stitch vias to inner ground layers to maintain low digital-to-analog crosstalk and ensure the 800 MHz input bandwidth is realized in practice.
Bộ thay thế dễ dàng lắp đặt cho LTC2172IUKG-12 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với LTC2172IUKG-12 (cùng hình factor và footprint) — khác nhau ở Package, Operating Temperature Range, Input Type, Resolution, Supply Voltage.
LTC2172IUKG-14
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LTC2171IUKG-12
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →LTC2170IUKG-12
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →LTC2171CUKG-12
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →LTC2170CUKG-12
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →LTC2172CUKG-12
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →LTC2172IUKG-12 Tỷ lệ tối đa & tính chất điện
| Architecture | Pipelined, simultaneous sampling |
| Độ phân giải | 12 bits |
| Number of Channels | 4 |
| Sampling Rate (max) | 65 Msps per channel |
| Input Bandwidth (full power) | 800 MHz |
| Input Type | Differential |
| Digital Output Interface | LVDS / CMOS selectable |
| Configuration Interface | Serial SPI port |
| Shutdown Modes | Channel Shutdown and Nap |
| Pin Compatibility | Pin-compatible with 14-bit LTC2170-14/2171-14/2172-14 |
| Hộp | 52-pin QFN (UKG), 7 mm x 8 mm with exposed pad |
| Kiểu lắp đặt | Surface Mount |
| Operating Temperature Range (I grade) | -40C to +85C |
| RoHS Compliance | Compliant (PBF suffix) |
| Cấp MSL | 1 |
Cấu hình chân LTC2172IUKG-12
| Chân 1 | AIN1+ — Channel 1 positive analog input |
| Chân 2 | AIN1- — Channel 1 negative analog input |
| Chân 3 | AIN2+ — Channel 2 positive analog input |
| Chân 4 | AIN2- — Channel 2 negative analog input |
| Chân 5 | AIN3+ — Channel 3 positive analog input |
| Chân 6 | AIN3- — Channel 3 negative analog input |
| Chân 7 | AIN4+ — Channel 4 positive analog input |
| Chân 8 | AIN4- — Channel 4 negative analog input |
| Chân 9 | VREF — Voltage reference bypass |
| Chân 10 | CM — Common-mode voltage output |
| Chân 11 | SENSE — Reference programming pin |
| Chân 12 | GND — Ground (analog) |
| Chân 13 | AVDD1 — Analog 1.8V supply |
| Chân 14 | GND — Ground (analog) |
| Chân 15 | AVDD2 — Analog 1.8V supply |
| Chân 16 | GND — Ground (analog) |
| Chân 17 | AVDD3 — Analog 1.8V supply |
| Chân 18 | GND — Ground (analog) |
| Chân 19 | CLK+ — Differential clock positive input |
| Chân 20 | CLK- — Differential clock negative input |
| Chân 21 | GND — Ground (clock) |
| Chân 22 | OVDD — Output driver supply |
| Chân 23 | D1A+ — Channel 1 LVDS data output (positive) |
| Chân 24 | D1A- — Channel 1 LVDS data output (negative) |
| Chân 25 | D1B+ — Channel 1 LVDS data output (positive) |
| Chân 26 | D1B- — Channel 1 LVDS data output (negative) |
| Chân 27 | D2A+ — Channel 2 LVDS data output (positive) |
| Chân 28 | D2A- — Channel 2 LVDS data output (negative) |
| Chân 29 | D2B+ — Channel 2 LVDS data output (positive) |
| Chân 30 | D2B- — Channel 2 LVDS data output (negative) |
| Chân 31 | D3+ — Channel 3 LVDS data output (positive) |
| Chân 32 | D3- — Channel 3 LVDS data output (negative) |
| Chân 33 | GND — Ground (digital) |
| Chân 34 | OVDD — Output driver supply |
| Chân 35 | D4+ — Channel 4 LVDS data output (positive) |
| Chân 36 | D4- — Channel 4 LVDS data output (negative) |
| Chân 37 | FR+ — Frame output LVDS positive |
| Chân 38 | FR- — Frame output LVDS negative |
| Chân 39 | CLKOUT+ — Clock output LVDS positive |
| Chân 40 | CLKOUT- — Clock output LVDS negative |
| Chân 41 | OVDD — Output driver supply |
| Chân 42 | GND — Ground (digital) |
| Chân 43 | OVDD — Output driver supply |
| Chân 44 | GND — Ground (digital) |
| Chân 45 | CS — SPI chip select (active low) |
| Chân 46 | SCK — SPI serial clock |
| Chân 47 | SDI — SPI serial data input |
| Chân 48 | SDO — SPI serial data output |
| Chân 49 | OGND — Ground (output drivers) |
| Chân 50 | OVDD — Output driver supply |
| Chân 51 | NC — Not connected (per datasheet) |
| Chân 52 | NC — Not connected (per datasheet) |
Ứng dụng tiêu biểu
LTC2172IUKG-12 phù hợp cho 6 Áp dụngs: Cellular Base Station Receiver, Phased Array Radar Digitizer, Medical Ultrasound Beamforming, Multi-Channel Data Acquisition System, Portable Instrumentation, MIMO Wireless Research Platform.
Cellular Base Station Receiver
The LTC2172IUKG-12's four simultaneous-sampling 12-bit 65 Msps ADC channels with 800 MHz input bandwidth make it well suited for multi-antenna cellular base-station receiver digitizers. Its pipelined architecture and LVDS outputs preserve time-domain coherence across channels, which is essential for diversity combining, MIMO decoding, and beamforming in LTE and 5G NR radio units. Compared with discrete ADC + FPGA solutions, the integrated quad channel reduces PCB area by approximately 60% while keeping aggregate power around 400 mW.
Được đề xuất
Phased Array Radar Digitizer
Phased-array radar systems require precise, simultaneous sampling of multiple antenna channels to compute accurate beamsteering vectors. The LTC2172IUKG-12 delivers four matched ADC channels sampling at 65 Msps with sub-sample aperture matching, ensuring phase coherence across the array. The 800 MHz analog input bandwidth supports direct IF sampling at intermediate frequencies up to 200 MHz, eliminating an analog downconversion stage and reducing system cost.
Được đề xuất
Medical Ultrasound Beamforming
In ultrasound imaging front ends, multiple transducer channels must be sampled synchronously to support digital beamforming. The LTC2172IUKG-12's four 65 Msps 12-bit channels with simultaneous sampling provide the time-aligned data streams required for aperture summation and delay-and-sum beamforming algorithms. The channel-level shutdown mode enables power reduction when only subsets of channels are active, important for portable or battery-powered ultrasound carts.
Được đề xuất
Multi-Channel Data Acquisition System
Automated test equipment and multi-channel DAQ systems benefit from the LTC2172IUKG-12's four integrated 12-bit 65 Msps channels, which replace four discrete ADCs and a synchronization FPGA. The integrated SPI configuration port allows gain, offset, and channel-enable adjustments at runtime, while LVDS outputs minimize digital switching noise in dense 16- or 32-channel chassis. The 12-bit resolution is appropriate for vibration, acoustic, and general-purpose industrial measurements.
Được đề xuất
Portable Instrumentation
The LTC2172IUKG-12's approximately 400 mW total power dissipation and channel-level shutdown modes make it suitable for battery-powered handheld oscilloscopes, spectrum analyzers, and field test gear. Four 65 Msps channels support up to 260 Msps aggregate sample rate, sufficient for 100 MHz bandwidth portable instruments. The industrial temperature grade (-40C to +85C) ensures operation across outdoor field environments and automotive test conditions.
Được đề xuất
MIMO Wireless Research Platform
Academic and industrial wireless researchers building 4x4 or 8x8 MIMO prototypes can use the LTC2172IUKG-12 to digitize antenna arrays with synchronized sampling across all channels. The pin-compatible 14-bit LTC2172IUKG-14 variant allows the same platform to support higher-resolution measurements when studying modem performance. The integrated quad-channel form factor is space-efficient on SDR reference designs and software-defined radio platforms.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho LTC2172IUKG-12 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | LTC2172IUKG-14 | LTC2171IUKG-12 | LTC2170IUKG-12 | LTC2171CUKG-12 | LTC2170CUKG-12 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 52-QFN (UKG) 7x8 mm | 52-QFN (UKG) 7x8 mm - same | 52-QFN (UKG) 7x8 mm - same | 52-QFN (UKG) 7x8 mm - same | 52-QFN (UKG) 7x8 mm - same | 52-QFN (UKG) 7x8 mm - same |
| Resolution | 12 bit | 14 bit (+2 bits) | 12 bit | 12 bit | 12 bit | 12 bit |
| Sampling Rate | 65 Msps | 65 Msps | 40 Msps (-38%) | 25 Msps (-62%) | 40 Msps (-38%) | 25 Msps (-62%) |
| Number of Channels | 4 | 4 | 4 | 4 | 4 | 4 |
| Input Bandwidth | 800 MHz | 800 MHz | 800 MHz | 800 MHz | 800 MHz | 800 MHz |
| Operating Temperature | -40C to +85C (I grade) | -40C to +85C (I grade) | -40C to +85C (I grade) | -40C to +85C (I grade) | 0C to +70C (C grade) | 0C to +70C (C grade) |
| Digital Output | LVDS / CMOS | LVDS / CMOS | LVDS / CMOS | LVDS / CMOS | LVDS / CMOS | LVDS / CMOS |
| Lifecycle Status | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy |
Bảo phân biệt quan trọng
- Pin-compatible resolution upgrade to 14-bit within the same family (vsLTC2172IUKG-14)
- Same UKG package for power/cost optimization when full 65 Msps is unused (vsLTC2171IUKG-12)
- Single-package 4-channel simultaneous sampling eliminates multi-ADC skew (vsDiscreet 4x single-channel ADC solution)
Ghi chú thiết kế
The 52-pin QFN (UKG) package requires a continuous ground plane beneath the exposed thermal pad and multiple stitching vias to inner ground layers. Per Analog Devices layout guidelines, place input traces symmetrically and route differential pairs with matched lengths to within 0.5 mm to preserve 800 MHz analog bandwidth and minimize second-harmonic distortion. Separate analog and digital ground regions should join at a single point near the ADC ground pins.
Estimated: with 65 Msps LVDS output, each output pair toggles at 390 Mbps, producing common-mode currents that can couple into analog inputs if ground returns are not isolated. Maintain at least 5 mm spacing between LVDS output traces and analog input traces, and use a solid uninterrupted ground plane beneath the analog section. The CLK+ and CLK- differential clock traces should be length-matched to within 0.13 mm to minimize aperture timing skew across channels.
Decouple each AVDD and OVDD pin with a 0.1 uF X7R ceramic capacitor placed within 2 mm of the pin, supplemented by a 10 uF bulk capacitor near the package. Per the datasheet, the 1.8V analog supply should be derived from a low-noise LDO such as the ADP150 rather than a switching converter to avoid spurious tones coupling into the ADC's analog front end. Power sequencing should bring up AVDD before OVDD, with the difference never exceeding 0.3V.
Common design errors include leaving the SPI port floating at power-up (which causes indeterminate output format selection) and forgetting to enable the internal reference via the SENSE pin. Always pull CS high through a 100 kohm resistor to default the SPI to a high-impedance state. Do not exceed the absolute maximum differential clock input of 2 Vpp; use an AC-coupled clock with center voltage at the analog common-mode level.
Thông tin tuân thủ
RoHS compliance confirmed by the #PBF suffix per the verified DigiKey product listing. REACH compliance status is presumed for ADI standard parts but should be verified with the manufacturer for the specific lot. Not AEC-Q100 qualified (industrial-grade IC); not intended for automotive safety applications.
