LTC2267IUJ-14 - 14-Bit 105Msps Dual ADC | Analog Devices
MPN: LTC2267IUJ-14 ✓ Hoạt độngLTC2267IUJ-14 Tóm tắt
A pipelined ADC is a high-speed successive-approximation architecture in which each conversion stage resolves a few bits and passes the residue to the next stage, enabling 100+ Msps sampling while keeping per-stage gain and bandwidth requirements modest. The LTC2267-14 family targets low-power instrumentation, communications baseband, and diversity-radio IF digitizing where both channels must be captured simultaneously and with deterministic latency.
Key features include 105Msps guaranteed sampling rate, ±0.3 LSB (typ) DNL, ±1 LSB (typ) INL with no missing codes over temperature, and 1.2 LSB RMS transition noise. According to the LTC2268-14 / LTC2267-14 / LTC2266-14 datasheet, the parts deliver 800 MHz full-power sample-and-hold bandwidth, configurable 2-lane / 1-lane LVDS output serialization (16-, 14-, or 12-bit), shutdown and nap modes, plus a serial SPI port for configuration. Pin-compatible 14-bit and 12-bit family members (LTC2268-14 / LTC2267-14 / LTC2266-14) simplify system scaling across speed grades.
Typical applications include diversity/MIMO receiver IF digitizing, cellular base-station baseband sampling, software-defined radio (SDR), handheld signal analyzers, and low-power multi-channel data acquisition front-ends. The 6mm × 6mm QFN-40 package and SPI control interface support compact, low-power PCB designs.
When designing with this part, ensure the analog input drive network presents the correct 50 Ω differential termination to preserve SFDR. Decouple AVDD and DVDD rails independently, and use the shutdown/nap pins for power gating between sample bursts. The LTC2267IUJ-14 is the industrial (-40 °C to +85 °C) temperature grade; the LTC2267CUJ-14 is the commercial variant.
Bộ thay thế dễ dàng lắp đặt cho LTC2267IUJ-14 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với LTC2267IUJ-14 (cùng hình factor và footprint) — khác nhau ở Package, Number of Channels, Resolution, RoHS Status, Input Type.
LTC2266IUJ-14
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LTC2268IUJ-14
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →LTC2267IUJ-12
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LTC2267CUJ-14
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →LTC2264IUJ-14
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →LTC2267IUJ-14 Tỷ lệ tối đa & tính chất điện
| Độ phân giải | 14 bits |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Tỷ lệ lấy mẫu | 105 Msps |
| Architecture | Pipelined |
| INL (typical) | ±1 LSB |
| DNL (typical) | ±0.3 LSB |
| Transition Noise | 1.2 LSB RMS |
| Missing Codes | No missing codes over temperature |
| Full-Power Input Bandwidth | 800 MHz |
| Digital Output Interface | Serial LVDS (2-lane / 1-lane, 16/14/12-bit serialization) |
| Configuration Interface | Serial SPI port |
| Power Modes | Shutdown, Nap, Full-speed |
| Hộp | 40-lead 6×6 mm QFN (UJ package) |
| Khoảng nhiệt độ hoạt động | -40 °C to +85 °C (IUJ industrial grade) |
| Pin-Compatible Family | LTC2268-14, LTC2266-14, LTC2268-12, LTC2267-12, LTC2266-12 |
Cấu hình chân LTC2267IUJ-14
| Chân 1 | GND — Ground |
| Chân 2 | AVDD — Analog supply voltage |
| Chân 3 | VA+ — Differential analog input (channel A, positive) |
| Chân 4 | VA- — Differential analog input (channel A, negative) |
| Chân 5 | GND — Ground |
| Chân 6 | REFTAPA — Reference decoupling, channel A |
| Chân 7 | REFBUFA — Reference buffer, channel A |
| Chân 8 | REFMA — Reference ground, channel A |
| Chân 9 | REFTPA — Reference top, channel A |
| Chân 10 | REFBPA — Reference bottom, channel A |
| Chân 11 | CLK_A — Sample clock, channel A |
| Chân 12 | SHDN — Shutdown (active high) |
| Chân 13 | MODE — Configuration: tied to VDD or GND selects SPI/parallel mode |
| Chân 14 | SDI — SPI serial data input |
| Chân 15 | SCK — SPI serial clock |
| Chân 16 | CS — SPI chip select (active low) |
| Chân 17 | SDO — SPI serial data output |
| Chân 18 | OGND — Output driver ground (LVDS) |
| Chân 19 | OVDD — Output driver supply (LVDS) |
| Chân 20 | OUTA_N — Channel A LVDS negative output |
| Chân 21 | OUTA_P — Channel A LVDS positive output |
| Chân 22 | FR_N — Frame LVDS negative output |
| Chân 23 | FR_P — Frame LVDS positive output |
| Chân 24 | DCO_N — Data clock LVDS negative output |
| Chân 25 | DCO_P — Data clock LVDS positive output |
| Chân 26 | OUTB_N — Channel B LVDS negative output |
| Chân 27 | OUTB_P — Channel B LVDS positive output |
| Chân 28 | OVDD — Output driver supply (LVDS) |
| Chân 29 | OGND — Output driver ground (LVDS) |
| Chân 30 | GND — Ground |
| Chân 31 | REFTPB — Reference top, channel B |
| Chân 32 | REFMA — Reference ground, channel B |
| Chân 33 | REFBPB — Reference bottom, channel B |
| Chân 34 | REFBUFB — Reference buffer, channel B |
| Chân 35 | REFTAPB — Reference decoupling, channel B |
| Chân 36 | GND — Ground |
| Chân 37 | VB- — Differential analog input (channel B, negative) |
| Chân 38 | VB+ — Differential analog input (channel B, positive) |
| Chân 39 | AVDD — Analog supply voltage |
| Chân 40 | GND — Ground (exposed pad) |
Ứng dụng tiêu biểu
LTC2267IUJ-14 phù hợp cho 6 Áp dụngs: Diversity / MIMO Receiver IF Digitizing, Cellular Base-Station Baseband Sampling, Software-Defined Radio (SDR) Front-End, Handheld Spectrum / Signal Analyzer, Medical Ultrasound Imaging Receiver, Multi-Channel Industrial Data Acquisition.
Diversity / MIMO Receiver IF Digitizing
The LTC2267IUJ-14's dual simultaneous-sampling 14-bit channels at 105 Msps directly digitize two diversity or MIMO IF chains with deterministic channel-to-channel latency, eliminating skew mismatch that degrades MRC combining gain. Its 800 MHz full-power analog input bandwidth supports IF frequencies up to 200+ MHz for multiband cellular base-station receivers and 4G/5G diversity modules. The serial LVDS output minimizes the FPGA pin count, critical when four or more diversity channels share a single FPGA. Configure the part via SPI to 2-lane LVDS for highest throughput, and use the shutdown pin between sample bursts to drop quiescent power in TDD systems.
Được đề xuất
Cellular Base-Station Baseband Sampling
Base-station radios need multi-channel baseband capture with high SFDR and tight gain matching. The LTC2267IUJ-14 provides ±1 LSB INL and 1.2 LSB RMS transition noise, which directly preserves EVM in LTE and 5G NR baseband. Its dual-channel integration halves PCB area versus two single-channel ADCs and ensures identical gain/offset drift between channels. The SPI port lets calibration coefficients be loaded per channel at startup, and the nap mode enables per-channel power gating in non-contiguous carrier aggregation scenarios.
Được đề xuất
Software-Defined Radio (SDR) Front-End
Wideband SDRs need an ADC that can directly sample HF/VHF/UHF IF frequencies without aliasing. The LTC2267IUJ-14's 800 MHz input bandwidth and 105 Msps throughput capture signals up to 200 MHz in a single Nyquist zone, simplifying the analog anti-alias filter. The 14-bit resolution provides ~84 dB SNR (theoretical 6.02×14+1.76), sufficient for amateur and tactical SDR receivers. The serial LVDS interface connects cleanly to common SDR FPGA boards and reduces board complexity versus parallel CMOS ADCs of equivalent speed.
Được đề xuất
Handheld Spectrum / Signal Analyzer
Portable spectrum analyzers need low-power, compact dual-channel ADCs that digitize both the IF and a reference channel for ratiometric correction. The LTC2267IUJ-14's low power (compared to 125 Msps parts) extends battery runtime, while its dual channels let designers share the analog anti-alias filter between signal and reference paths. The shutdown and nap modes allow aggressive duty-cycling between sweep segments, and the 1.2 LSB RMS noise floor keeps the analyzer's displayed average noise level (DANL) low.
Được đề xuất
Medical Ultrasound Imaging Receiver
Ultrasound receivers require 64-256 simultaneous receive channels, where each ADC must be small and low-power. The LTC2267IUJ-14's 40-QFN 6×6 mm footprint and dual-channel integration support dense channel-array PCB layouts. The 105 Msps rate captures up to 35 MHz of RF bandwidth, sufficient for 5-10 MHz clinical ultrasound transducers after beamforming. The serial LVDS output reduces routing congestion on the channel board, and the SPI port allows per-channel gain/offset trim to equalize beamforming performance.
Được đề xuất
Multi-Channel Industrial Data Acquisition
Industrial DAQ systems digitize strain gauge, vibration, and acoustic signals from many channels at once. The LTC2267IUJ-14's dual 14-bit channels and 800 MHz input bandwidth accommodate both high-speed vibration (turbomachinery monitoring) and lower-speed analog inputs (temperature-compensated strain gauges). The industrial -40 to +85 °C rating supports factory-floor deployment. The serial SPI port and nap-mode power gating allow the host MCU to power down idle ADC channels and wake them on demand, reducing system power in large channel-count installations.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho LTC2267IUJ-14 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | LTC2266IUJ-14 | LTC2268IUJ-14 | LTC2267IUJ-12 | LTC2267CUJ-14 | LTC2264IUJ-14 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 40-QFN (6x6) | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same |
| Resolution | 14 bits | 14 bits | 14 bits | 12 bits | 14 bits | 14 bits |
| Sampling Rate | 105 Msps | 80 Msps | 125 Msps | 105 Msps | 105 Msps | 105 Msps (single-channel family member) |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 1 (single-channel) |
| Input Bandwidth | 800 MHz | 800 MHz | 800 MHz | 800 MHz | 800 MHz | 800 MHz |
| Output Interface | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS |
| Operating Temperature | -40°C to +85°C (industrial) | -40°C to +85°C | -40°C to +85°C | -40°C to +85°C | 0°C to +70°C (commercial) | -40°C to +85°C |
| Configuration Interface | SPI | SPI | SPI | SPI | SPI | SPI |
Bảo phân biệt quan trọng
- Pin-compatible speed scaling across 80/105/125 Msps and 12/14-bit resolution (vsLTC2266IUJ-14 / LTC2268IUJ-14 / LTC2267IUJ-12)
- Dual simultaneous-sampling channels in one package (vsDiscrete dual-ADC board with two single-channel ADCs)
- 800 MHz analog input bandwidth enables direct IF sampling (vsLower-bandwidth ADCs (e.g., 250 MHz typical))
Ghi chú thiết kế
Differential analog inputs must be driven with a 50 Ω termination network (typically a 100 Ω across the differential pair or 50 Ω to a center-tapped transformer). Driving the inputs single-ended or with mismatched impedance degrades SFDR by 10-15 dB. Use a wideband RF transformer (e.g., ADT1-1WT, Mini-Circuits TC1-1T+) with center-tapped secondary to provide the differential drive and bias the common-mode voltage per the datasheet.
Route LVDS output pairs (OUTA_P/N, OUTB_P/N, DCO_P/N, FR_P/N) as 100 Ω differential traces with continuous reference ground, length-matched within 5 ps to preserve setup/hold margins at the FPGA. Decouple AVDD (analog supply) and OVDD (LVDS driver supply) with separate ferrite beads and 10 µF + 0.1 µF local capacitors. Place the SPI bus (SDI/SCK/CS/SDO) away from analog inputs to avoid digital coupling into the analog front-end.
The exposed thermal pad (pin 40 / GND on the bottom of the QFN) must be soldered directly to a continuous ground plane with multiple thermal vias (≥9 vias, 0.3 mm drill) for heat dissipation. A continuous ground keepout is required under the analog input traces to prevent digital return currents from injecting noise. Reference decoupling pins (REFTAPA, REFBUFA, REFTPA, etc.) require star-ground returns to the ADC ground pad with 0.1 µF and 10 µF local bypass.
Jitter on the CLK_A sampling clock directly degrades SNR: for an analog input at frequency fIN, SNR_jitter = 20·log10(1 / (2π · fIN · tj)). To preserve the 14-bit SNR at 70 MHz IF, total sample-clock jitter must be below ~0.5 ps RMS. Use an ultra-low-jitter clock generator (e.g., AD9516-4 or HMC7044) and route CLK_A as a 50 Ω controlled-impedance trace with a series damping resistor close to the ADC pin.
Thông tin tuân thủ
Lead-free per #PBF suffix. RoHS and REACH compliance confirmed by Analog Devices product page (https://www.analog.com/en/products/ltc2267-14.html). AEC-Q100 not applicable - this part is not automotive qualified; for automotive-grade ADCs see ADI's AEC-Q100 catalog.
