PIC24FJ128GB206-I/MR - 16-bit 32MHz 128KB Flash USB MCU | Microchip
MPN: PIC24FJ128GB206-I/MR ✓ Hoạt độngPIC24FJ128GB206-I/MR Tóm tắt
What is a 16-bit microcontroller? A microcontroller (MCU) is a single-chip computer containing a CPU core, non-volatile program memory (Flash), volatile working memory (RAM), and a rich set of on-chip peripherals such as timers, communication interfaces, and analog blocks. The PIC24FJ128GB206-I/MR belongs to the broader taxonomy: microcontroller -> 16-bit MCU -> PIC24F family -> PIC24FJ GB2 sub-family -> Microchip 16-bit secure connectivity MCU.
Key features include 128 KB (43K x 24) of self-programmable Flash, 96 KB of RAM, USB 2.0 OTG with dual-role (host or peripheral), integrated hardware crypto engine with key storage, a true random number generator, multiple UART/SPI/I2C peripherals, a 10-bit ADC, and a parallel master port for graphics displays. The XLP variant provides nanoWatt deep-sleep currents suitable for battery-powered applications.
Architecturally, the device uses a modified Harvard RISC core with a 16-bit data path and 24-bit instruction width, supporting 32 MIPS at 32 MHz. Integrated peripherals are mapped via a Peripheral Pin Select (PPS) system, allowing flexible function-to-pin routing. The hardware crypto engine accelerates AES, DES, 3DES, SHA-1, SHA-256, and HMAC operations offloaded from the CPU.
Typical applications include USB peripherals (HID, CDC, mass storage), secure IoT endpoints, battery-powered wearables, graphics display controllers, secure token/authentication devices, and industrial data loggers with on-board encryption.
When designing, allocate adequate decoupling (100 nF + 4.7 µF) near each VDD pin and follow Microchip's PGEC/PGED layout guidelines. The parallel master port shares pins with several peripherals - planning the pin map early avoids late-stage rework.
This page synthesizes distributor pricing, drop-in same-family alternatives, and design notes not consolidated on any single manufacturer or distributor page.
Bộ thay thế dễ dàng lắp đặt cho PIC24FJ128GB206-I/MR — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với PIC24FJ128GB206-I/MR (cùng hình factor và footprint) — khác nhau ở Package, Maximum CPU Speed, ADC, Family, Mounting Type.
PIC24FJ128GB206T-I/MR
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →PIC24FJ256GB206-I/MR
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
PIC24FJ128DA206-I/MR
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →PIC24FJ128GA606-I/MR
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
PIC24FJ128GA106-I/MR
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →PIC24FJ128GB206-I/MR Tỷ lệ tối đa & tính chất điện
| Core | PIC 16-bit RISC (modified Harvard) |
| Family | PIC24FJ GB2 (eXtreme Low Power) |
| Maximum CPU Speed | 32 MIPS at 32 MHz |
| Program Flash | 128 KB (43K x 24 words) |
| RAM | 96 KB |
| Supply Voltage (VDD) | 2.5 V / 3.3 V |
| Nhiệt độ hoạt động | -40 C to +85 C (Industrial, "-I") |
| Hộp | 64-pin VQFN (9x9 mm) with exposed pad |
| USB | USB 2.0 On-The-Go, dual-role (host or peripheral) |
| Crypto Engine | Integrated AES / DES / 3DES / SHA / HMAC |
| Random Number Generator | Hardware TRNG |
| ADC | 10-bit, multi-channel |
| Graphics | Parallel Master Port for external display |
| Kiểu lắp đặt | Surface Mount |
| Trạng thái RoHS | Compliant |
Cấu hình chân PIC24FJ128GB206-I/MR
| Chân 1 | RA0 — GPIO / analog input / peripheral pin select |
| Chân 2 | RA1 — GPIO / analog input / peripheral pin select |
| Chân 3 | RA2 — GPIO / analog input / peripheral pin select |
| Chân 4 | RA3 — GPIO / analog input / peripheral pin select |
| Chân 5 | RA4 — GPIO / peripheral pin select |
| Chân 6 | RA5 — GPIO / peripheral pin select |
| Chân 7 | RA6 — GPIO / peripheral pin select |
| Chân 8 | RA7 — GPIO / peripheral pin select |
| Chân 9 | RB0 — GPIO / peripheral pin select |
| Chân 10 | RB1 — GPIO / peripheral pin select |
| Chân 11 | RB2 — GPIO / peripheral pin select |
| Chân 12 | RB3 — GPIO / peripheral pin select |
| Chân 13 | RB4 — GPIO / peripheral pin select |
| Chân 14 | RB5 — GPIO / peripheral pin select |
| Chân 15 | RB6 — GPIO / peripheral pin select |
| Chân 16 | RB7 — GPIO / peripheral pin select |
| Chân 17 | RC0 — GPIO / peripheral pin select |
| Chân 18 | RC1 — GPIO / peripheral pin select |
| Chân 19 | RC2 — GPIO / peripheral pin select |
| Chân 20 | RC3 — GPIO / peripheral pin select |
| Chân 21 | RC4 — GPIO / peripheral pin select |
| Chân 22 | RC5 — GPIO / peripheral pin select |
| Chân 23 | RC6 — GPIO / peripheral pin select |
| Chân 24 | RC7 — GPIO / peripheral pin select |
| Chân 25 | RD0 — GPIO / peripheral pin select |
| Chân 26 | RD1 — GPIO / peripheral pin select |
| Chân 27 | RD2 — GPIO / peripheral pin select |
| Chân 28 | RD3 — GPIO / peripheral pin select |
| Chân 29 | RD4 — GPIO / peripheral pin select |
| Chân 30 | RD5 — GPIO / peripheral pin select |
| Chân 31 | RD6 — GPIO / peripheral pin select |
| Chân 32 | RD7 — GPIO / peripheral pin select |
| Chân 33 | VDD — Positive supply (2.5 V / 3.3 V) |
| Chân 34 | VSS — Ground |
| Chân 35 | RE0 — GPIO / peripheral pin select |
| Chân 36 | RE1 — GPIO / peripheral pin select |
| Chân 37 | RE2 — GPIO / peripheral pin select |
| Chân 38 | RE3 — GPIO / peripheral pin select |
| Chân 39 | RE4 — GPIO / peripheral pin select |
| Chân 40 | RE5 — GPIO / peripheral pin select |
| Chân 41 | RE6 — GPIO / peripheral pin select |
| Chân 42 | RE7 — GPIO / peripheral pin select |
| Chân 43 | RF0 — GPIO / peripheral pin select |
| Chân 44 | RF1 — GPIO / peripheral pin select |
| Chân 45 | RF2 — GPIO / peripheral pin select |
| Chân 46 | RF3 — GPIO / peripheral pin select |
| Chân 47 | RF4 — GPIO / peripheral pin select |
| Chân 48 | RF5 — GPIO / peripheral pin select |
| Chân 49 | RF6 — GPIO / peripheral pin select |
| Chân 50 | RF7 — GPIO / peripheral pin select |
| Chân 51 | RG0 — GPIO / peripheral pin select |
| Chân 52 | RG1 — GPIO / peripheral pin select |
| Chân 53 | RG2 — GPIO / peripheral pin select (D+) |
| Chân 54 | RG3 — GPIO / peripheral pin select (D-) |
| Chân 55 | RG6 — GPIO / peripheral pin select |
| Chân 56 | RG7 — GPIO / peripheral pin select |
| Chân 57 | RG8 — GPIO / peripheral pin select |
| Chân 58 | RG9 — GPIO / peripheral pin select |
| Chân 59 | VDD — Positive supply (2.5 V / 3.3 V) |
| Chân 60 | VSS — Ground |
| Chân 61 | OSC1 — Crystal oscillator input |
| Chân 62 | OSC2 — Crystal oscillator output |
| Chân 63 | MCLR — Master clear reset (active low) |
| Chân 64 | EP — Exposed thermal pad (must be soldered to VSS for thermal dissipation) |
Ứng dụng tiêu biểu
PIC24FJ128GB206-I/MR phù hợp cho 6 Áp dụngs: USB HID / CDC Peripheral Devices, Secure IoT Sensor Endpoints, Battery-Powered Wearables and Fitness Bands, Graphics Display Controllers (TFT via PMP), Secure Authentication Tokens and Crypto Keys, Industrial Data Loggers with Encryption.
USB HID / CDC Peripheral Devices
The PIC24FJ128GB206-I/MR fits USB HID and CDC peripheral designs because its integrated USB 2.0 Full-Speed transceiver, 96 KB RAM, and 32 MIPS core remove the need for an external PHY or MCU companion. According to the Microchip GB2 datasheet, the USB OTG module supports HID, CDC, mass storage, and vendor-class device stacks in ROM-free configuration, with the 128 KB Flash holding both the USB stack and the application. The hardware crypto engine can simultaneously run AES-128 on packets, providing inline encryption for HID authentication tokens. Developers should allocate a 1.5 kB endpoint buffer and use the PPS system to free D+/D- for application I/O.
Được đề xuất
Secure IoT Sensor Endpoints
The PIC24FJ128GB206-I/MR is well suited to secure battery-powered IoT sensor endpoints because the eXtreme Low Power (XLP) technology delivers sub-uA sleep currents, the hardware AES/SHA engine accelerates TLS handshakes off-CPU, and the 96 KB RAM handles fragmented TLS records without external memory. According to Microchip's XLP datasheet section, the deep-sleep current can drop below 100 nA with RTC running, enabling multi-year coin-cell operation. The integrated TRNG provides the entropy source for cryptographic keys, removing the need for an external secure element in many low-risk deployments.
Được đề xuất
Battery-Powered Wearables and Fitness Bands
The PIC24FJ128GB206-I/MR suits wearables because the XLP sleep modes and 32 MHz/32 MIPS performance envelope let the device wake, sample sensors, perform on-chip AES-encrypted logging, and return to deep sleep within milliseconds - all on a coin cell. The 64-pin VQFN at 9x9 mm keeps the PCB footprint small, and the rich PPS pin mapping lets designers route SPI/I2C sensors, an OLED display, and a USB charging interface without bus contention. The 96 KB RAM also enables on-device buffering of up to 10 minutes of sensor data before transmission.
Được đề xuất
Graphics Display Controllers (TFT via PMP)
The PIC24FJ128GB206-I/MR drives small TFT displays through the Parallel Master Port (PMP) and benefits from 96 KB of RAM which is enough to host a full QVGA frame buffer (320x240x16 = 153 KB requires external RAM) or a partial WQVGA buffer (e.g., 160x240x16 = 76.5 KB) entirely on-chip. The PMP supports 8-bit and 16-bit data widths and address-latching for direct connection to ILI9341-style controllers. Combined with the 32 MIPS core, this enables smooth UI updates at 30+ FPS for menus, charts, and simple animations.
Được đề xuất
Secure Authentication Tokens and Crypto Keys
The PIC24FJ128GB206-I/MR is ideal for hardware authentication tokens because the integrated hardware AES-128/192/256, SHA-256, and HMAC engine, combined with the true random number generator and secure key storage, provide the building blocks for FIDO2 / TOTP / HMAC-based challenge-response tokens. The 32 MIPS core responds to a challenge in under 50 ms, and the XLP sleep currents allow the token to sit idle for years on a single CR2032. The USB OTG port doubles as the host interface, supporting HID and CCID smart-card-style protocols natively.
Được đề xuất
Industrial Data Loggers with Encryption
The PIC24FJ128GB206-I/MR fits industrial encrypted data loggers because the wide operating temperature (-40 C to +85 C), large RAM (96 KB) for buffering, and integrated AES/SHA engine for at-rest encryption eliminate the need for a separate crypto co-processor. According to the Microchip family datasheet, multiple UART, SPI, and I2C interfaces permit simultaneous connection to industrial sensors (Modbus, I2C sensors, SPI ADCs). The 128 KB Flash hosts a real-time OS or scheduler plus the encrypted file system, simplifying BOM and PCB layout in space-constrained DIN-rail enclosures.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho PIC24FJ128GB206-I/MR — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | PIC24FJ128GB206T-I/MR | PIC24FJ256GB206-I/MR | PIC24FJ128DA206-I/MR | PIC24FJ128GA606-I/MR | PIC24FJ128GA106-I/MR |
|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 64-VQFN (9x9 mm, MR) | 64-VQFN (9x9 mm, MR) - same | 64-VQFN (MR) - same | 64-VQFN (MR) - same | 64-VQFN (MR) - same | 64-VQFN (MR) - same |
| Program Flash | 128 KB | 128 KB | 256 KB | 128 KB | 128 KB | 128 KB |
| USB Support | USB 2.0 OTG (host + device) | USB 2.0 OTG (host + device) | USB 2.0 OTG (host + device) | USB 2.0 device (no OTG) | USB 2.0 device (no OTG) | No USB |
| Hardware Crypto Engine | Yes (AES / DES / SHA / HMAC) | Yes (AES / DES / SHA / HMAC) | Yes (AES / DES / SHA / HMAC) | No | No | No |
| TRNG (True RNG) | Yes | Yes | Yes | No | No | No |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
Bảo phân biệt quan trọng
- Largest RAM in GB2 family (vsPIC24FJ128DA206-I/MR)
- Integrated hardware crypto engine and TRNG (vsPIC24FJ128GA606-I/MR)
- USB On-The-Go dual-role (vsPIC24FJ128GA106-I/MR)
- Industrial temperature grade and XLP sleep currents (vsPIC24FJ128GB202-I/MM (28-pin cousin))
Ghi chú thiết kế
Place a 100 nF ceramic decoupling capacitor within 5 mm of each VDD pin and a bulk 4.7 uF tantalum or ceramic capacitor near the package. According to Microchip PIC24F hardware design guidelines, inadequate decoupling on the 2.5 V / 3.3 V rails is the leading cause of USB enumeration failures and crypto-engine lock-ups. For battery designs, switch to the internal LDO mode and disable the voltage regulator if not required.
The 64-pin VQFN has an exposed thermal pad that must be soldered to a continuous VSS copper pour with at least 8 thermal vias to the inner ground plane. The PGECx/PGEDx programming pins are sensitive to crosstalk - per Northern Software's PIC24FJ128GB206 application note, add a 20 pF capacitor from PGECx to VSS close to the IC if programming reliability issues appear. Keep USB D+/D traces 90-ohm differential, length-matched within 2 mm, and routed over a continuous ground plane.
Do not enable the parallel master port (PMP), USB, and crypto engine simultaneously without budgeting for combined current - peak USB enumeration plus AES can briefly exceed 60 mA. The PPS (Peripheral Pin Select) registers must be unlocked and locked around configuration writes; forgetting this causes silent peripheral failures. For OTA firmware updates, partition Flash into a 64 KB bootloader and 64 KB application slot to allow fail-safe rollback.
Route USB D+ (RG2) and D- (RG3) as a 90 ohm differential pair with no splits, keep total length under 50 mm, and place the 15 kohm pull-down on D- as close to the MCU as possible. The integrated USB transceiver requires a 1 uF capacitor on VBUS for OTG host mode SRP detection. For CE/FCC emissions compliance, place a common-mode choke on D+/D- if the cable exits the enclosure.
Thông tin tuân thủ
RoHS and lead-free per Microchip product page. Not AEC-Q100 qualified - consult Microchip automotive PIC24F portfolio for automotive-grade variants. Halogen-free status not explicitly listed in provided data.
