PIC24FJ128GB406-I/MR - 16-bit MCU, 128KB Flash, USB OTG, 64-QFN | Microchip
MPN: PIC24FJ128GB406-I/MR ✓ Hoạt độngPIC24FJ128GB406-I/MR Tóm tắt
What is a PIC24F microcontroller? The PIC24F is a 16-bit modified-Harvard MCU family from Microchip positioned between 8-bit PIC16/PIC18 parts and 32-bit PIC32 parts. Within the PIC taxonomy it sits in the middle tier, delivering higher performance than 8-bit parts while retaining low-power XLP modes. It belongs to the broader class of microcontrollers (MCUs) inside embedded processors, which are themselves a category of integrated circuits used for digital control. The PIC24FJ128GB406 adds a hardware cryptography engine, full-speed USB On-The-Go (OTG), an LCD segment driver, and extreme low-power (XLP) sleep currents below 1 uA in deep sleep.
Key features include the integrated AES/Hardware Crypto peripheral (suitable for 128/192/256-bit AES in hardware), a 16-channel 10-bit A/D converter with 500 ksps throughput, four UART modules, three SPI, three I2C, a Parallel Master Port, and a Peripheral Pin Select (PPS) system that remaps digital peripherals to any I/O. The wide 2.0 V to 3.6 V supply range allows direct Li-Ion battery operation, and the 16 MIPS core plus DMA controller keep the CPU off-load for USB isochronous traffic.
The architecture pairs a 16-bit ALU with a C compiler-friendly instruction set, deterministic interrupt latency, and a small 31-element instruction shadow set for real-time tasks. The 128 KB Flash supports self-programming, and the ICSP/In-Circuit Serial Programming header lets the part be programmed on the board.
Typical applications include USB HID/CDC peripherals, secure IoT sensor nodes, electronic access control with LCD keypads, low-cost AES-secured data loggers, and battery-powered industrial HMIs. The combination of integrated crypto, USB OTG, and LCD driver removes the need for an external crypto companion chip in many designs.
When designing with this part, ensure the Vbus/Vbuson and D+/D- traces are length-matched within 150 mils and routed to a USB-compliant 90-ohm differential impedance. Place a 1 uF X7R bypass within 3 mm of every VDDA/Vcap pin and connect the exposed pad to a continuous ground plane for thermal dissipation.
This page synthesizes live distributor pricing, drop-in same-package alternatives, and practical design notes drawn from the manufacturer datasheet and reference designs - information not collated on a single distributor product page.
Bộ thay thế dễ dàng lắp đặt cho PIC24FJ128GB406-I/MR — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với PIC24FJ128GB406-I/MR (cùng hình factor và footprint) — khác nhau ở Package, Operating Temperature, ADC, Family, Program Memory (Flash).
PIC24FJ256GB406-I/MR
✅ Drop-In ⚠️ Thông số chưa được xác minh📋 Tham chiếu thay thế (không có trong danh mục)
PIC24FJ128GA406-I/MR
✅ Drop-In ⚠️ Thông số chưa được xác minh📋 Tham chiếu thay thế (không có trong danh mục)
PIC24FJ128GB410-I/MR
✅ Drop-In ⚠️ Thông số chưa được xác minh📋 Tham chiếu thay thế (không có trong danh mục)
PIC24FJ256GB410-I/MR
✅ Drop-In ⚠️ Thông số chưa được xác minh📋 Tham chiếu thay thế (không có trong danh mục)
PIC24FJ128GB204-I/MR
✅ Drop-In ⚠️ Thông số chưa được xác minh📋 Tham chiếu thay thế (không có trong danh mục)
PIC24FJ1024GB606-I/MR
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
PIC24FJ128GB406-I/MR Tỷ lệ tối đa & tính chất điện
| Core | PIC24F 16-bit modified-Harvard |
| Max CPU Speed | 32 MHz / 16 MIPS |
| Program Flash | 128 KB (43K x 24 words) |
| Data RAM | 16 KB |
| Hardware Cryptography | Integrated AES 128/192/256-bit engine |
| USB | USB 2.0 Full-Speed OTG with dedicated DMA |
| LCD Driver | Integrated segment LCD driver (up to 128 segments) |
| ADC | 10-bit, up to 16 channels, 500 ksps |
| Timers | 5 x 16-bit, 2 x 32-bit |
| UART / SPI / I2C | 4 / 3 / 3 modules |
| Parallel Master Port (PMP) | Yes |
| Peripheral Pin Select (PPS) | Yes (remappable digital peripherals) |
| Điện áp cung cấp | 2.0 V to 3.6 V |
| XLP Sleep Current | < 1 uA (deep sleep, RTCC + SRAM retention) |
| Nhiệt độ hoạt động | -40C to +85C (industrial, -I suffix) |
| Hộp | 64-pin QFN (9 x 9 x 0.9 mm) with exposed pad |
| Kiểu lắp đặt | Surface Mount |
| Cấp MSL | 3 (per JEDEC J-STD-020) |
| Trạng thái RoHS | Compliant (lead-free) |
Cấu hình chân PIC24FJ128GB406-I/MR
| Chân 1 | RA0 — Port A bit 0 (analog-capable) |
| Chân 2 | RA1 — Port A bit 1 (analog-capable) |
| Chân 3 | RA2 — Port A bit 2 (analog-capable) |
| Chân 4 | RA3 — Port A bit 3 (analog-capable) |
| Chân 5 | RA4 — Port A bit 4 (analog-capable) |
| Chân 6 | RA5 — Port A bit 5 (analog-capable) |
| Chân 7 | RA6 — Port A bit 6 (analog-capable) |
| Chân 8 | RA7 — Port A bit 7 (analog-capable) |
| Chân 9 | RB0 — Port B bit 0 (PPS-capable) |
| Chân 10 | RB1 — Port B bit 1 (PPS-capable) |
| Chân 11 | RB2 — Port B bit 2 (PPS-capable) |
| Chân 12 | RB3 — Port B bit 3 (PPS-capable) |
| Chân 13 | RB4 — Port B bit 4 (PPS-capable) |
| Chân 14 | RB5 — Port B bit 5 (PPS-capable) |
| Chân 15 | RB6 — Port B bit 6 (PPS-capable, ICD PGEC) |
| Chân 16 | RB7 — Port B bit 7 (PPS-capable, ICD PGED) |
| Chân 17 | RC0 — Port C bit 0 (PPS-capable) |
| Chân 18 | RC1 — Port C bit 1 (PPS-capable, OSC2) |
| Chân 19 | RC2 — Port C bit 2 (PPS-capable, OSC1) |
| Chân 20 | VSS — Ground reference |
| Chân 21 | RC3 — Port C bit 3 (PPS-capable) |
| Chân 22 | RC4 — Port C bit 4 (PPS-capable) |
| Chân 23 | RC5 — Port C bit 5 (PPS-capable) |
| Chân 24 | RC6 — Port C bit 6 (PPS-capable) |
| Chân 25 | RC7 — Port C bit 7 (PPS-capable) |
| Chân 26 | RC8 — Port C bit 8 (PPS-capable) |
| Chân 27 | RC9 — Port C bit 9 (PPS-capable) |
| Chân 28 | VDD — Digital supply (2.0-3.6 V) |
| Chân 29 | RD0 — Port D bit 0 (PMP-capable) |
| Chân 30 | RD1 — Port D bit 1 (PMP-capable) |
| Chân 31 | RD2 — Port D bit 2 (PMP-capable) |
| Chân 32 | RD3 — Port D bit 3 (PMP-capable) |
| Chân 33 | RD4 — Port D bit 4 (PMP-capable) |
| Chân 34 | RD5 — Port D bit 5 (PMP-capable) |
| Chân 35 | RD6 — Port D bit 6 (PMP-capable) |
| Chân 36 | RD7 — Port D bit 7 (PMP-capable) |
| Chân 37 | RE0 — Port E bit 0 (PMP-capable) |
| Chân 38 | RE1 — Port E bit 1 (PMP-capable) |
| Chân 39 | RE2 — Port E bit 2 (PMP-capable) |
| Chân 40 | RE3 — Port E bit 3 (PMP-capable) |
| Chân 41 | RE4 — Port E bit 4 (PMP-capable) |
| Chân 42 | RE5 — Port E bit 5 (PMP-capable) |
| Chân 43 | RE6 — Port E bit 6 (PMP-capable) |
| Chân 44 | RE7 — Port E bit 7 (PMP-capable) |
| Chân 45 | RF0 — Port F bit 0 (PMP-capable) |
| Chân 46 | RF1 — Port F bit 1 (PMP-capable) |
| Chân 47 | RF2 — Port F bit 2 (PMP-capable) |
| Chân 48 | RF3 — Port F bit 3 (PMP-capable) |
| Chân 49 | RF4 — Port F bit 4 (PMP-capable) |
| Chân 50 | RF5 — Port F bit 5 (PMP-capable) |
| Chân 51 | RF6 — Port F bit 6 (PMP-capable) |
| Chân 52 | RF7 — Port F bit 7 (PMP-capable) |
| Chân 53 | RG0 — Port G bit 0 |
| Chân 54 | RG1 — Port G bit 1 |
| Chân 55 | RG2 — Port G bit 2 (D+ USB) |
| Chân 56 | RG3 — Port G bit 3 (D- USB) |
| Chân 57 | VUSB3V3 — USB internal 3.3 V regulator output |
| Chân 58 | VBUS — USB VBUS detect input |
| Chân 59 | D- — USB D- differential data line |
| Chân 60 | D+ — USB D+ differential data line |
| Chân 61 | ID — USB OTG ID pin (host/device detect) |
| Chân 62 | VCAP — 1.8 V core LDO output (bypass 10 uF + 0.1 uF) |
| Chân 63 | VDD — Digital supply (2.0-3.6 V) |
| Chân 64 | VSS — Ground reference (and EP thermal pad) |
Ứng dụng tiêu biểu
PIC24FJ128GB406-I/MR phù hợp cho 6 Áp dụngs: USB HID / CDC Peripheral, Secure IoT Sensor Node, Electronic Access Control with LCD Keypad, AES-Secured Industrial Data Logger, USB-Connected Medical Accessory, Battery-Powered Industrial HMI with Touch.
USB HID / CDC Peripheral
The PIC24FJ128GB406's integrated USB 2.0 Full-Speed OTG peripheral with dedicated DMA channels makes it a drop-in choice for USB HID keyboards, mice, and CDC virtual COM port bridges. With 16 MIPS and 16 KB RAM, the core runs HID report descriptors or CDC line-coding handlers without CPU saturation, while the XLP deep-sleep below 1 uA lets battery-powered HID devices idle for months. The hardware AES engine on the 'GB' family allows secure HID firmware updates without external crypto ICs. A typical BOM pairs the MCU with a USB micro-B connector, ESD protection array, and 3.3 V LDO; the 64-QFN's exposed pad should be soldered to a full ground plane for thermal and EMI reasons. Reference designs in the PIC24F USB starter kit (DM320003) demonstrate enumeration and Suspend/Resume.
Được đề xuất
Secure IoT Sensor Node
The hardware AES-128/192/256 engine and XLP deep-sleep below 1 uA make the PIC24FJ128GB406 ideal for battery-powered IoT sensor nodes that must encrypt telemetry before transmission over Wi-Fi, LoRa, or Bluetooth companion modules. The 10-bit 500 ksps ADC samples temperature, humidity, or analog sensors while the DMA-fed AES engine encrypts batches of data with the CPU in sleep, achieving sub-microamp average current. The 128 KB Flash stores TLS certificates or LoRaWAN MAC keys, and the parallel pin remap (PPS) lets the SPI bus connect to a LoRa transceiver (SX1276) on any GPIO. Operate from a single 3.0 V CR123A cell, regulated by a 3.3 V LDO with 100 mA headroom.
Được đề xuất
Electronic Access Control with LCD Keypad
The integrated segment LCD driver (up to 128 segments) on the PIC24FJ128GB406 removes the need for an external LCD controller in PIN-code keypads, RFID card readers, and door-lock HMIs. The hardware AES engine validates 128-bit AES card tags in tens of microseconds while the LCD shows status icons and the keypad matrix scans up to 100 keys via the integrated charge-sharing ADC or interrupt-on-change. The XLP sleep current below 1 uA lets the lock run for years on four AA cells. The 64-QFN package exposes 5 UART/SPI/I2C blocks, allowing simultaneous connection to a real-time clock, RFID reader, and door-strike relay driver. Use the dedicated RTCC module to maintain wall-clock time during sleep.
Được đề xuất
AES-Secured Industrial Data Logger
Industrial data loggers for vibration, temperature, or pressure often need both hardware AES to protect proprietary test data and a high-speed ADC to capture fast transients. The PIC24FJ128GB406's hardware AES engine accelerates bulk encryption of log payloads by 5-10x versus a software-only implementation, freeing the CPU for the 500 ksps 10-bit ADC scan plus SD-card writes via SPI. The 16 KB RAM buffers one full sector before flush, and the 128 KB Flash stores the encrypted log header and calibration constants. The 2.0-3.6 V supply runs directly from a Li-Ion or 3.3 V industrial rail, while the -40 to +85C industrial temperature rating supports factory-floor deployment. The Peripheral Pin Select (PPS) system lets the SPI bus for SD cards share pins with the UART diagnostic port via firmware remap.
Được đề xuất
USB-Connected Medical Accessory
The PIC24FJ128GB406's combination of USB OTG, hardware AES, and XLP sleep makes it suitable for USB-powered medical accessories such as glucose meters, pulse oximeters, and connected pill dispensers. The hardware AES-256 engine meets HIPAA-aligned encryption-at-rest requirements without external crypto ICs, while the 10-bit ADC reads sensor analog front-ends. USB bus-power eliminates batteries for the charging circuit; the integrated USB transceivers and pull-up/pull-down resistors keep the BOM minimal. The 64-QFN exposes enough pins for both USB and a segment LCD showing glucose readings. The industrial -40 to +85C temperature rating covers clinical and home use environments.
Được đề xuất
Battery-Powered Industrial HMI with Touch
Combined with the PIC24FJ128GB406's CTMU (Charge Time Measurement Unit) and Peripheral Pin Select, designers can build a battery-powered HMI with up to 24 capacitive touch buttons plus a segment LCD, drawing only 5-15 uA average current. The hardware AES engine secures configuration parameters stored in Flash, while the USB OTG port is used for firmware updates rather than daily operation. The 64-QFN's exposed pad allows adequate heat dissipation for the 8 mA active current at 32 MHz. The wide 2.0-3.6 V supply range lets the HMI run from two AA cells directly, regulated by an internal 1.8 V LDO that requires only a 10 uF + 0.1 uF bypass on Vcap.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho PIC24FJ128GB406-I/MR — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | PIC24FJ256GB406-I/MR | PIC24FJ128GA406-I/MR | PIC24FJ128GB410-I/MR | PIC24FJ256GB410-I/MR | PIC24FJ128GB204-I/MR | PIC24FJ1024GB606-I/MR |
|---|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 64-QFN (9x9 mm) MR | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same |
| Flash | 128 KB | 256 KB | 128 KB | 128 KB | 256 KB | 128 KB | 1024 KB |
| RAM | 16 KB | 16 KB | 16 KB | 16 KB | 16 KB | 8 KB | 32 KB |
| Hardware AES | Yes (128/192/256-bit) | Yes | No | No | No | Yes (smaller pkg) | Yes |
| USB OTG | Yes (Full-Speed) | Yes | Yes | Yes | Yes | Yes | Yes |
| LCD Driver | Yes (segment) | Yes | Yes | Yes | Yes | Yes | Yes |
| Max CPU Speed | 32 MHz / 16 MIPS | 32 MHz / 16 MIPS | 32 MHz / 16 MIPS | 32 MHz / 16 MIPS | 32 MHz / 16 MIPS | 32 MHz / 16 MIPS | 32 MHz / 16 MIPS |
| Supply Voltage | 2.0 V to 3.6 V | 2.0-3.6 V | 2.0-3.6 V | 2.0-3.6 V | 2.0-3.6 V | 2.0-3.6 V | 2.0-3.6 V |
Bảo phân biệt quan trọng
- Integrated hardware AES-128/192/256 crypto engine (vsPIC24FJ128GA406-I/MR)
- Doubles program Flash to 256 KB while preserving pinout (vsPIC24FJ256GB406-I/MR)
- Massively scalable Flash (1 MB) without leaving the same package (vsPIC24FJ1024GB606-I/MR)
Ghi chú thiết kế
Estimated: the 64-QFN (9x9) package requires a continuous ground plane beneath the exposed pad. Use 0.5 oz copper with 0.3 mm via stitching at 1.5 mm pitch connecting the EP to the inner ground pour. This keeps the junction-to-ambient thermal resistance at the datasheet value of approximately 28 C/W and prevents thermal throttling during sustained 32 MHz operation. Routing the USB D+/D- lines as a 90-ohm differential pair (length-matched within 150 mils) is mandatory for USB-IF compliance.
Place a 10 uF X7R + 0.1 uF NP0/C0G capacitor pair within 3 mm of the VCAP pin (1.8 V core LDO output). Use a low-ESR ceramic for the 10 uF and route a wide VDD/VSS trace to minimize inductance. The USB VUSB3V3 pin needs an additional 4.7 uF decoupling capacitor. For USB suspend/resume peaks, ensure the upstream 3.3 V LDO can source at least 100 mA without droop, otherwise VBUS-detect logic may falsely detect a detach event.
Do not leave the MCLR pin floating - tie it to VDD through a 10 kohm pull-up. The ICD PGEC/PGED pins (RB6/RB7) must be left disconnected in production to avoid debugger contention. The Peripheral Pin Select (PPS) registers must be unlocked before remapping; lock the registers again afterward or stray writes during EMI events can corrupt pin assignments. Finally, if USB OTG host mode is unused, tie the ID pin to ground.
Keep analog AVSS/AVDD separated from digital VSS/VDD with a ferrite bead or 0-ohm resistor, and place AVSS adjacent to the analog pins (RA0-RA7). Route the 32.768 kHz crystal traces within 5 mm of SOSCO/SOSCI with a guard ring tied to analog ground. For LCD segment outputs, route with 5-8 mil traces and add a ground keep-out underneath segment pads to minimize capacitive loading and cross-talk.
Thông tin tuân thủ
RoHS compliant per Microchip product page. Industrial -40C to +85C temperature grade (-I suffix). Not AEC-Q100 qualified - not recommended for automotive applications; choose PIC24FJ...-E automotive variants if available. Halogen-free status not explicitly stated in provided data.
