5CSEBA2U19C8N vs 5CSEBA2U19C6N 比較

詳細並排比較 5CSEBA2U19C8N 由 Altera 與 5CSEBA2U19C6N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 5CSEBA2U19C8N 5CSEBA2U19C6N
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Family Cyclone V SE SoC FPGA Cyclone V SE SoC FPGA
Series 5CSEA2 —
Device Variant 5CSEBA2 (25K logic elements, dual ARM Cortex-A9) —
Core Architecture Dual ARM Cortex-A9 MPCore with CoreSight —
HPS Maximum Frequency 600 MHz —
FPGA Logic Elements 25,000 —
Embedded Memory (M10K) 1,400 Kb (typical for 25K LE variant) —
DSP Blocks Variable-precision DSP Variable-precision DSP
Process Technology 28 nm low-power TSMC 28 nm low-power
Core Supply Voltage 1.1 V —
Memory Controller Support DDR2, DDR3, LPDDR2 —
High-Speed Transceivers Present (Cyclone V SE family feature) —
PLLs Multiple (per Cyclone V SE device handbook) —
封裝 484-pin UBGА (19x19 mm) 484-pin UBGA (19x19 mm)
安裝類型 Surface Mount Surface Mount
工作溫度 0C to +85C (commercial) —
MSL 等級 3 (per JEDEC J-STD-020, assumed for 484-BGA) —
RoHS 狀態 Compliant Compliant
Logic Elements — 25 K
Hard Processor System — Dual ARM Cortex-A9 MPCore with CoreSight
HPS Maximum Clock Frequency — 925 MHz
Operating Temperature Grade — Commercial (other)
Memory Interfaces — DDR2, DDR3, LPDDR2 with ECC
HPS Peripherals — GbE, USB 2.0 OTG, SATA, CAN, UART, SPI, I2C, SD/SDIO/MMC
L2 Cache — 512 KB shared
L1 Cache per Core — 32 KB I-cache + 32 KB D-cache
FPGA-to-HPS Bridges — AXI-32/AXI-64, FPGA-to-SDRAM ports

資料表與資源

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