5CSEBA4U19I7SN vs 5CSEBA4U19I7LN 比較
詳細並排比較 5CSEBA4U19I7SN 由 Intel 與 5CSEBA4U19I7LN 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | 5CSEBA4U19I7SN | 5CSEBA4U19I7LN |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Series | Cyclone V SE SoC FPGA | — |
| Device Family | Cyclone V | — |
| Logic Elements | 40,000 | 40K |
| Hard Processor System (HPS) | Single ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 800 MHz | 925 MHz |
| 封裝 | 484-pin UBG A (19x19 mm) | 484-pin UFBGA (19x19 mm, 0.8 mm pitch) |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| 工作溫度 | -40C to +100C (Industrial) | — |
| Process Node | 28 nm low-power | — |
| Supply Voltage (Core) | 1.1 V (typical) | — |
| I/O Standards Supported | LVTTL, LVCMOS, LVDS, SSTL, HSTL (Cyclone V I/O family) | — |
| Embedded Memory | [DATA_NEEDED: total Kbits of M9K blocks] | — |
| 18x18 Hardware Multipliers | [DATA_NEEDED: count] | — |
| PLLs | [DATA_NEEDED: count] | [DATA_NEEDED: PLL count per family datasheet] |
| Transceivers | Not applicable (SE family, transceiver-less) | — |
| PCI Express Hard IP | Gen1 capable (rootport/endpoint) | — |
| DDR Memory Support | DDR2/DDR3/LPDDR2 via HPS and FPGA fabric | — |
| RoHS 狀態 | Compliant | Compliant |
| Family | — | Cyclone V SE SoC FPGA |
| Hard Processor System | — | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| FPGA Logic Performance | — | up to 925 MHz DSP / 300 MHz logic |
| Embedded Memory (M10K) | — | [DATA_NEEDED: total M10K bits] |
| DSP Blocks (18x18 Multipliers) | — | 56 |
| Memory Controller | — | DDR2/DDR3/LPDDR2 with ECC (hardened in HPS) |
| HPS Peripherals | — | UART, SPI, I2C, USB 2.0 OTG, EMAC, SD/MMC, NAND, GPIO |
| Process Technology | — | TSMC 28 nm low-power |
| Operating Temperature (Industrial) | — | -40C to +100C (I7 grade, inferred from MPN suffix) |
| Supply Voltage (core) | — | 1.1 V typical (Cyclone V family) |
| Configuration Scheme | — | Serial (EPCS) or Quad-Serial Flash |