5CSXFC6C6U23I7LN vs 5CSXFC6C6U23C8NES 比較

詳細並排比較 5CSXFC6C6U23I7LN 由 Altera 與 5CSXFC6C6U23C8NES 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
5CSXFC6C6U23I7LN 5CSXFC6C6U23I7LN - Cyclone V SX SoC FPGA 110K LE | Altera

5CSXFC6C6U23I7LN - Cyclone V SX SoC FPGA 110K LE | Altera

5CSXFC6C6U23I7LN ✓ 啟用中
Intel
5CSXFC6C6U23C8NES 5CSXFC6C6U23C8NES - Cyclone V SX SoC FPGA 110K LE | Intel

5CSXFC6C6U23C8NES - Cyclone V SX SoC FPGA 110K LE | Intel

5CSXFC6C6U23C8NES ✓ 啟用中

規格比較

參數 5CSXFC6C6U23I7LN 5CSXFC6C6U23C8NES
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Family Cyclone V SX SoC FPGA Cyclone V SX
Device Variant 5CSXFC6C6U23 —
Logic Elements 110K 110,000
Hard Processor System Dual ARM Cortex-A9 MPCore with CoreSight —
Maximum HPS Clock Frequency 925 MHz —
封裝 672-UBGA (23x23 mm) 672-pin UBGА (23x23 mm)
工作溫度 -40C to +100C (Industrial) —
Process Technology 28 nm low-power —
Embedded Memory [DATA_NEEDED: total Kbits] —
DSP Blocks Variable-precision, supports 18x18 and 27x27 multipliers —
Transceivers Integrated high-speed transceivers —
HPS Peripherals USB, GbE, SD/SDIO/MMC, UART, SPI, I2C —
Memory Interfaces DDR3, DDR2, LPDDR2 —
I/O Standards LVDS, LVCMOS, SSTL —
Configuration HPS boot from NAND/NOR/SD/eMMC; FPGA via Quartus Prime —
RoHS 狀態 Compliant Compliant
安裝類型 Surface Mount (BGA) Surface Mount (BGA)
Device Type — SoC FPGA (FPGA + ARM Cortex-A9 HPS)
Hard Processor Subsystem — Dual ARM Cortex-A9 MPCore with CoreSight
HPS Clock Frequency (max) — 600 MHz
Process Node — 28 nm TSMC low-power
Embedded Memory (M10K + MLAB) — 5,140 Kbits (approx)
DSP Blocks (18x19 multipliers) — 112
User I/O Pins — 224
Speed Grade — 8 (commercial)
工作接面溫度 — 0C to +85C (commercial)
External Memory Interfaces — DDR2, DDR3, LPDDR2
Hard PCIe Gen2 Controllers — 2

資料表與資源

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