5M40ZE64C4N vs 5M40ZE64C5N 比較
詳細並排比較 5M40ZE64C4N 由 Intel 與 5M40ZE64C5N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | 5M40ZE64C4N | 5M40ZE64C5N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | MAX V | — |
| Logic Elements (LE) | 32 | 40 |
| User Flash Memory | 4 Kbit | — |
| Pin-to-Pin Delay (tPD1) | 7.5 ns | — |
| Maximum Internal Frequency | 184 MHz | 118.3 MHz |
| Number of I/O Pins | 30 (approx.) | — |
| Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Bank Voltage | 1.8 V / 2.5 V / 3.3 V | — |
| Process Technology | 0.18 µm flash-based CMOS | — |
| Configuration Memory | Non-volatile flash (internal) | Flash (non-volatile) |
| Programmable Pull-up Resistors | Yes (per-pin, internal) | — |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) - in-system programmable |
| 工作溫度 | 0 °C to +85 °C (commercial) | 0C to +85C (commercial) |
| 封裝 | EQFP-64 (Plastic Enhanced QFP, 64 pins) | 64-pin EQFP (Plastic Enhanced Thin QFP) with exposed thermal pad |
| 安裝類型 | Surface Mount | Surface Mount |
| MSL 等級 | 3 (per JEDEC J-STD-020) | — |
| RoHS 狀態 | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Series | — | MAX V |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Macrocells | — | 32 |
| Maximum User I/Os | — | 54 |
| Propagation Delay (tPD1) | — | 7.5 ns |
| Supply Voltage - Core | — | 1.8 V (internal) |
| External Supply Voltage | — | 3.3 V |
| I/O Voltage Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V LVCMOS, LVTTL |
| User Flash Memory (UFM) | — | Yes (on-chip non-volatile) |