5M40ZM64C4N vs 5M40ZM64C5N 比較
詳細並排比較 5M40ZM64C4N 由 Altera 與 5M40ZM64C5N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | 5M40ZM64C4N | 5M40ZM64C5N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | MAX V | MAX V |
| Logic Elements | 40 | — |
| Macro Cells | 32 | — |
| Number of I/O Pins | 30 (max user I/O) | — |
| Number of Logic Array Blocks | 2 LABs (16 macrocells each) | — |
| Core Voltage VCCINT | 1.8 V (1.71 V to 1.89 V) | — |
| I/O Voltage VCCIO | 1.2 V to 3.3 V (multi-voltage) | — |
| Maximum Internal Frequency | 184.1 MHz | 118.3 MHz |
| Pin-to-Pin Logic Delay (tPD) | 7.5 ns | 7.5 ns |
| Propagation Delay (max) | 7.5 ns | — |
| 工作溫度 | 0 °C to +85 °C (commercial) | — |
| 封裝 | 64-MBGA (Micro FineLine BGA), 4.5 x 4.5 mm | 64-ball MBGA, 5 mm × 5 mm |
| 安裝類型 | Surface Mount (BGA) | Surface Mount (BGA) |
| Configuration Memory | Flash (non-volatile, instant-on) | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) ISP |
| RoHS 狀態 | Compliant | Compliant |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| Device Logic Elements | — | 40 |
| Macrocells | — | 32 |
| Supply Voltage - Core (VCCINT) | — | 1.8 V |
| I/O Voltage Banks | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V tolerant |
| Programmable I/O Pins | — | 30 (approximate, per MAX V 5M40Z datasheet family) |
| User Flash Memory | — | 8 Kbits |
| Configuration Method | — | Non-volatile flash, instant-on, single-chip |
| Standby Current (ICCSTBY) | — | 55 µA typical |
| 工作溫度範圍 | — | 0 °C to +85 °C (commercial) |