5M570ZE64I5N vs 5M240ZM68I5N 比較

詳細並排比較 5M570ZE64I5N 由 Intel 與 5M240ZM68I5N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Intel
5M570ZE64I5N 5M570ZE64I5N - 570 LE MAX V CPLD, 64-EQFP | Intel

5M570ZE64I5N - 570 LE MAX V CPLD, 64-EQFP | Intel

5M570ZE64I5N ✓ 啟用中
Intel
5M240ZM68I5N 5M240ZM68I5N - 68-Ball Industrial MAX V CPLD | Intel

5M240ZM68I5N - 68-Ball Industrial MAX V CPLD | Intel

5M240ZM68I5N ✓ 啟用中

規格比較

參數 5M570ZE64I5N 5M240ZM68I5N
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Series MAX V MAX V
Programmable Type In System Programmable —
Number of Logic Elements / Blocks 570 —
Number of Macrocells 440 192
Number of User I/O 54 —
Propagation Delay tpd(1) Max 9 ns —
Internal Supply Voltage VCCINT 1.71 V to 1.89 V (1.8 V typical) —
工作溫度範圍 -40 C to +100 C (TJ) —
安裝類型 Surface Mount Surface Mount
封裝 / 外殼 64-TQFP Exposed Pad (EQFP-64) —
Supplier Device Package 64-EQFP (7x7 mm) —
Configuration Memory Non-volatile Flash Nonvolatile Flash
Programmable I/O Voltage Standards 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O) —
Programming Interface JTAG (IEEE 1149.1) —
RoHS 狀態 Compliant Compliant
Lead-Free Yes —
Device Type — CPLD (Complex Programmable Logic Device)
Logic Elements — 240
Propagation Delay (tPD) — 7.5 ns
Package Type — TFBGA-68
Number of Terminals — 68 (ball)
Package Code — TFBGA
Form of Terminal — Ball
Package Shape — Square
Operating Temperature Grade — Industrial
JTAG Interface — TMS, TDI, TDO, TCK (Bank 1)
Programming Method — JTAG / in-system programmable
供應電壓 — [DATA_NEEDED: VCCINT and VCCIO levels]
I/O Standards — Multiple (LVTTL, LVCMOS, SSTL, etc., per MAX V doc; PCI and 1.2 V LVCMOS excluded for JTAG pins)
Lead Free — Yes

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