A42MX24-2PLG84I vs A42MX09-2PLG84 比較
詳細並排比較 A42MX24-2PLG84I 由 Microchip Technology 與 A42MX09-2PLG84 由 Microchip Technology. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Microchip Technology
A42MX24-2PLG84I - 36K Gate Antifuse FPGA, 84-PLCC | Microchip
A42MX24-2PLG84I ✓ 啟用中規格比較
| 參數 | A42MX24-2PLG84I | A42MX09-2PLG84 |
|---|---|---|
| 品牌 | Microchip Technology | Microchip Technology |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | MX (42MX) | 42MX (MX FPGA) |
| System Gates | 36000 gates | 14000 |
| Logic Cells | 912 cells | 336 |
| User I/O | 72 | 72 |
| Technology | 0.45 um antifuse | 0.45 um antifuse |
| Core Architecture Voltage | 5.0 V | — |
| I/O Voltage Support | 3.3 V / 5.0 V mixed | — |
| Speed Grade | -2 | -2 |
| Programmability | One-Time Programmable (antifuse) | — |
| 工作溫度 | -40C to +85C (Industrial) | [DATA_NEEDED: operating temperature range] |
| 封裝 | 84-PLCC (J-Lead) | 84-LCC (J-Lead) / PLCC-84 |
| 安裝類型 | Surface Mount | Surface Mount |
| Configuration | No external boot device required | — |
| Dedicated Decode Blocks | D-modules (wide-input AND, CPLD-like) | — |
| RoHS 狀態 | Lead Free (per Kynix listing) | [DATA_NEEDED: RoHS status] |
| Packaging | Tray | — |
| Primary Applications | ASIC alternative, legacy PLD integration | — |
| Clock-to-Out | — | 5.6 ns |
| Internal Performance | — | up to 250 MHz (161 MHz / 269 MHz grade limits per FindIC) |
| Dual-Port SRAM | — | up to 2.5 kbits (family max), 5 ns access |
| FIFO Performance | — | 100 MHz (family) |
| Core Voltage | — | 3.3 V to 5 V (dual voltage, 0.45 um technology) |
| Supply Voltage Range | — | 3.0 V to 3.6 V and 4.5 V to 5.5 V |
| Programming Type | — | One-Time Programmable (antifuse), non-volatile |