ADC1213D080HN-C18 vs ADC1112D125HN-C18 比較
詳細並排比較 ADC1213D080HN-C18 由 Renesas Electronics 與 ADC1112D125HN-C18 由 Renesas Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Renesas Electronics
ADC1213D080HN-C18 - 12-bit 80MSPS Dual ADC with JESD204A | Renesas
ADC1213D080HN-C18 ✓ 啟用中Renesas Electronics
ADC1112D125HN-C18 - Dual 11-bit 125MSPS ADC, LVDS/CMOS | Renesas
ADC1112D125HN-C18 ✓ 啟用中規格比較
| 參數 | ADC1213D080HN-C18 | ADC1112D125HN-C18 |
|---|---|---|
| 品牌 | Renesas Electronics | Renesas Electronics |
| 類別 | ADC/DAC | ADC/DAC |
| 生命週期狀態 | 啟用中 | 啟用中 |
| 解析度 | 12 bit | 11-bit |
| Number of Channels | 2 (dual, simultaneous sampling) | 2 (dual, simultaneous sampling) |
| Sampling Rate per Channel | 80 MSPS | — |
| Architecture | Pipelined | — |
| Data Output Interface | JESD204A (serial, up to 3.125 Gbps lane) | — |
| 封裝 | 56-VFQFPN exposed pad (8x8 mm) | HVQFN-64 (8x8 mm with exposed thermal pad) |
| Analog Supply Voltage (AVDD) | 1.8 V | 3.0 V to 3.6 V |
| Digital/Drive Supply Voltage (DRVDD) | 3.3 V | — |
| Input Type | Differential / single-ended (configurable) | Single-ended analog inputs (per channel) |
| Input Bandwidth | [DATA_NEEDED: full-power input bandwidth MHz] | — |
| SNR | [DATA_NEEDED: SNR dBFS at fIN] | — |
| ENOB | [DATA_NEEDED: ENOB bits at fIN] | — |
| SFDR | [DATA_NEEDED: SFDR dBc] | — |
| Power Consumption | [DATA_NEEDED: power mW per channel at 80 MSPS] | — |
| 工作溫度範圍 | -40 C to +85 C (industrial) | -40 C to +85 C |
| Configuration Interface | SPI-compatible serial | — |
| 安裝類型 | Surface Mount | Surface Mount |
| MSL 等級 | 3 (per JEDEC J-STD-020) | 3 (168 hours) |
| RoHS 狀態 | Compliant | Compliant |
| Lead-Free | Yes | — |
| Sample Rate (Max) | — | 125 Msps |
| Digital I/O Supply (OVDD) | — | 1.8 V to 3.3 V |
| Output Interface | — | CMOS or LVDS DDR (selectable) |
| Reference | — | Internal programmable (0-6 dB in 1 dB steps) or external |
| Control Interface | — | SPI (3-wire, mode configuration) |
| Power-Down Mode | — | Yes, per-channel via SPI |