CDK8307BILP64 vs CDK8307AILP64 比較
詳細並排比較 CDK8307BILP64 由 MaxLinear 與 CDK8307AILP64 由 MaxLinear. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | CDK8307BILP64 | CDK8307AILP64 |
|---|---|---|
| 品牌 | MaxLinear | MaxLinear |
| 類別 | ADC/DAC | ADC/DAC |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Product Type | Octal Analog-to-Digital Converter (ADC) | — |
| 解析度 | 12-bit or 13-bit (programmable) | 12/13-bit (selectable) |
| Sample Rate (per channel) | 20 / 40 / 50 / 65 MSPS | — |
| Number of Channels | 8 | 8 (simultaneous sampling) |
| Total Power Dissipation | 280 mW | — |
| Data Output Interface | Serial LVDS | — |
| Input Type | Differential analog inputs (one per channel) | — |
| Reference | Internal (integrated bandgap reference) | Internal reference (integrated) |
| Clock Architecture | External reference clock with integrated PLL (x12 or x14 multiplication) | — |
| Control Interface | Serial control interface | Serial programming interface (SPI-style) |
| 封裝 | 64-pin QFN (LP suffix) | 64-pin QFN (ILP64) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度範圍 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: temperature range] |
| 供應電壓 | [DATA_NEEDED: supply voltage rating] | [DATA_NEEDED: supply voltage] |
| RoHS 狀態 | Compliant | Compliant |
| Sample Rate Range | — | 20 / 40 / 50 / 65 / 80 MSPS |
| Architecture | — | Pipelined ADC with proprietary core |
| Output Interface | — | Serial LVDS |
| Power Dissipation (Typ) | — | Ultra-low power (per-channel shutdown) |
| Shutdown Modes | — | Per-channel + full-chip idle (via external pin) |
| FPGA Compatibility | — | Designed to interface with major FPGA vendors |
| Original Brand | — | Cadeka / Exar (now MaxLinear) |