EP1810GC-35 vs EP1810GM883B 比較

詳細並排比較 EP1810GC-35 由 Altera 與 EP1810GM883B 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EP1810GC-35 EP1810GC-35 - UV PLD, 40ns, CMOS, CPGA68 | Altera / Rochester

EP1810GC-35 - UV PLD, 40ns, CMOS, CPGA68 | Altera / Rochester

EP1810GC-35 ⚠ 最後購買機會

規格比較

參數 EP1810GC-35 EP1810GM883B
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 最後購買 NRND
Device Type EPLD (Erasable Programmable Logic Device) —
Logic Family Altera Classic EPLD TTL-compatible I/O
Technology CMOS, UV-erasable EPROM cells CMOS, UV-erasable
封裝 CPGA-68 (Ceramic Pin Grid Array, 68-pin) —
腳位數 68 —
Propagation Delay (tpd max) 40 ns —
Maximum Inputs 64 —
Maximum Outputs 48 —
Macrocells 16 48
I/O Standard TTL-compatible —
Programming Method UV erasure + EPROM programming UV-erasable / Altera programming hardware
工作溫度 [DATA_NEEDED: operating temperature range] -55 °C to +125 °C (Military, MIL-STD-883B)
供應電壓 [DATA_NEEDED: VCC range] —
安裝類型 Through Hole Through-hole (PGA socket or PCB through-hole)
RoHS 狀態 Not applicable (legacy ceramic package) —
Lead-Free Status Not applicable —
Manufacturer (current source) Rochester Electronics (authorized Altera EPLD partner) —
Original Manufacturer Altera Corporation (now Intel FPGA) —
Device Family — EP1810 (Classic EPLD)
User Flip-Flops — Up to 64
Total Inputs — 60
Dedicated Inputs — 12
I/O Pins — 48 (bidirectional, tri-state)
Propagation Delay (tPD) — 50 ns max
Supply Voltage (VCC) — 4.5 V to 5.5 V
Package Type — Ceramic Pin Grid Array (PGA), 84 pins
Package Designator — GM (ceramic PGA)
Processing Level — MIL-STD-883B (Class B)
Lead-Free / RoHS — [DATA_NEEDED: lead-free status]

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