EP1810GC-35AB vs EP1810GM883 比較
詳細並排比較 EP1810GC-35AB 由 Altera 與 EP1810GM883 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810GC-35AB | EP1810GM883 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Family | Classic EPLD | — |
| Technology | CMOS EPROM | — |
| Number of Macrocells | 48 | — |
| Number of Usable Gates | 1200 | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Number of I/O Pins | 48 | — |
| Dedicated Input Pins | 12 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Toggle Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Package Type | Pin Grid Array (PGA), ceramic | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | -55C to +125C (MIL-STD-883 Class B) |
| Programming Method | UV-erasable EPROM, in-system via JTAG-like interface | — |
| RoHS 狀態 | unknown | [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] |
| Family | — | Classic EPLD (EP1810 series) |
| Device Type | — | UV-Erasable Programmable Logic Device (EPLD) |
| Macrocells | — | 48 |
| Dedicated Inputs | — | 12 |
| User I/O Pins | — | 48 |
| Total Terminals | — | 68 |
| Global Clocks | — | 4 |
| Supply Voltage (Vcc) | — | 4.5 V to 5.5 V (nominal 5 V) |
| Propagation Delay (tpd) | — | 45 ns (max) |
| Maximum Toggle Frequency (fmax) | — | [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] |
| Process Technology | — | CMOS, UV-erasable |
| 封裝 | — | 68-Pin Ceramic Pin Grid Array (PGA) |
| Screening | — | MIL-STD-883 Class B (suffix '883' denotes MIL processing) |
| 安裝類型 | — | Through-Hole (PGA socket) |
| Lead-Free | — | [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] |