EP1810JC-45 vs EP1810GM883B 比較
詳細並排比較 EP1810JC-45 由 Altera 與 EP1810GM883B 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810JC-45 | EP1810GM883B |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP1810 (Classic EPLD Family) | — |
| Macrocells | 48 | 48 |
| Equivalent Gates | 2100 gates | — |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 48 | 48 (bidirectional, tri-state) |
| Total User I/O | 60 | — |
| Propagation Delay (tpd) | 45 ns | — |
| 最大時脈頻率 | 33.3 MHz | — |
| Technology | CMOS, UV-erasable | CMOS, UV-erasable |
| Maximum Supply Voltage | 5.25 V | — |
| 封裝 | PLCC-68 (QCCJ, J-Lead, windowed ceramic) | — |
| 腳位數 | 68 | — |
| Package Code | QCCJ | — |
| Temperature Grade | Commercial | — |
| 安裝類型 | Surface Mount | Through-hole (PGA socket or PCB through-hole) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance not stated in verified data] | — |
| Device Family | — | EP1810 (Classic EPLD) |
| User Flip-Flops | — | Up to 64 |
| Total Inputs | — | 60 |
| Propagation Delay (tPD) | — | 50 ns max |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| 工作溫度 | — | -55 °C to +125 °C (Military, MIL-STD-883B) |
| Package Type | — | Ceramic Pin Grid Array (PGA), 84 pins |
| Package Designator | — | GM (ceramic PGA) |
| Processing Level | — | MIL-STD-883B (Class B) |
| Programming Method | — | UV-erasable / Altera programming hardware |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free status] |
| Logic Family | — | TTL-compatible I/O |