EP1810LC-25T vs EP1810JC-25 比較
詳細並排比較 EP1810LC-25T 由 Intel 與 EP1810JC-25 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810LC-25T | EP1810JC-25 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Family | Altera Classic EP1810 | Altera/Intel Classic EPLD (EP1810 series) |
| Device Type | EPLD (Erasable/OTP Complex PLD) | — |
| Macrocells | 48 (4 quadrants x 12 macrocells) | 48 |
| Usable Gates | Approx. 900 | — |
| Dedicated Inputs | 16 | 12 |
| Bidirectional I/O Pins | 48 | — |
| External Clocks | 4 | — |
| Propagation Delay (tPD) | 25 ns | 25 ns |
| Supply Voltage (VCC) | 5 V nominal | 4.75 V to 5.25 V |
| 工作溫度 | 0 °C to +70 °C (commercial) | -40 °C to 85 °C (industrial, per distributor listings) |
| 封裝 | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) | 28-pin ceramic DIP (J) with quartz window |
| 安裝類型 | Surface Mount | Through-hole |
| Technology | CMOS, UV-erasable / OTP | CMOS, UV-erasable (windowed ceramic DIP) |
| I/O Standard | TTL-compatible 5 V | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - confirm with manufacturer] | [DATA_NEEDED: RoHS compliance status] |
| Programming Tool | Altera MAX+PLUS II / Quartus Classic | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fMAX] |
| Input Lines | — | 60 (including I/O) |
| I/O Lines | — | 48 |
| External Clock Inputs | — | 4 |
| Erasure Method | — | UV light (windowed package) |
| 生命週期狀態 | — | NRND (Not Recommended for New Designs) |