EP1810LC-35 vs EP1810LC-45 比較
詳細並排比較 EP1810LC-35 由 Rochester Electronics 與 EP1810LC-45 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
EP1810LC-35 ⚠ 最後購買機會Rochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 Obsolete規格比較
| 參數 | EP1810LC-35 | EP1810LC-45 |
|---|---|---|
| 品牌 | Rochester Electronics | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Series | Classic EP1810 | — |
| Macrocells | 48 | — |
| Equivalent Gates | 900 usable / 2100 equivalent | — |
| Maximum Operating Frequency | 28.6 MHz | 22.2 MHz |
| Propagation Delay (tpd) | 35 ns (max, '-35' speed grade) | 45 ns |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| 封裝 | 68-pin PLCC (J-Lead) | 68-pin PLCC (J-lead) |
| 安裝類型 | Surface Mount (socketable) | Surface Mount (PLCC socket compatible) |
| 工作溫度 | 0C to +70C (commercial) | 0 °C to +70 °C (commercial) |
| I/O Pins | [DATA_NEEDED: I/O count exact] | — |
| Configuration Method | UV-erase + EPROM programmer | — |
| Programmable Interconnect | Centralized Programmable Interconnect Array (PIA) | — |
| Development Tool (legacy) | MAX+PLUS II / A+PLUS | — |
| RoHS 狀態 | [DATA_NEEDED] | [DATA_NEEDED: RoHS status of Rochester-sourced part] |
| Lead-Free | [DATA_NEEDED] | [DATA_NEEDED: lead-free finish] |
| Family | — | Altera Classic EPLD |
| Usable Gates | — | 900 |
| Macro Cells | — | 48 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Logic Array Blocks | — | 4 |
| Supply Voltage (Vcc) | — | 5 V (±5%) |
| Process Technology | — | 5 V CMOS EPROM |